Patents by Inventor Naoto Adachi
Naoto Adachi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20120300883Abstract: A demodulation circuit includes a hard decision process unit and a soft decision process unit. The hard decision process unit is configured to perform a hard decision process using a demodulated signal, and the demodulated signal is a demodulated received signal. The soft decision process unit is configured to determine a range of assignment with respect to a transitioning part in the demodulated signal, calculate a likelihood value of a bit, and perform a soft decision process.Type: ApplicationFiled: April 9, 2012Publication date: November 29, 2012Applicants: FUJITSU SEMICONDUCTOR LIMITED, FUJITSU LIMITEDInventors: Naoto ADACHI, Masataka UMEDA
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Patent number: 8300718Abstract: A demodulating circuit includes: a fast Fourier transform circuit which fast Fourier transforms a received signal and outputs a plurality of carrier signals; an output selecting circuit which selects at least two signals from the plurality of carrier signals, the at least two signals including a first signal modulated in accordance with a first modulation method and a second signal modulated in accordance with a second modulation method; an inverse fast Fourier transform circuit which inverse Fourier transforms transmission path characteristic values including a first transmission path characteristic value obtained based on the first signal and a second transmission path characteristic value obtained based on the second signal; and an FFT window control circuit which controls a position of an FFT window based on the inverse Fourier transformed transmission path characteristic values.Type: GrantFiled: May 18, 2010Date of Patent: October 30, 2012Assignee: Fujitsu Semiconductor LimitedInventor: Naoto Adachi
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Patent number: 8233553Abstract: A digital broadcast demodulator receives a tuner signal output from a tuner and carries out demodulation processing on the tuner signal by using an internal clock signal that is synchronized with a reference signal. The digital broadcast demodulator has an internal clock-signal generator and an internal clock frequency controller. The internal clock-signal generator generates the internal clock signal, and the internal clock frequency controller controls a frequency of the internal clock signal in accordance with a reception channel.Type: GrantFiled: June 27, 2008Date of Patent: July 31, 2012Assignee: Fujitsu LimitedInventors: Makoto Hamaminato, Naoto Adachi
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Patent number: 8229010Abstract: An OFDM signal is demodulated to generate a frequency domain signal in each of a plurality of branches. A diversity combining unit combines the demodulated signals respectively obtained in each of the branches. A clock recovery unit recovers the clock for the OFDM signal. A guard correlation unit detects the phase error of the OFDM signal. A decision unit identifies a branch having high reliability. A clock error correction unit generates a correction instruction, in accordance with the average value of the phase errors in the branch having high reliability. The clock recovery unit in each of the branches respectively corrects the error of the clock in accordance with the correction instruction.Type: GrantFiled: July 30, 2008Date of Patent: July 24, 2012Assignee: Fujitsu Semiconductor LimitedInventors: Naoto Adachi, Makoto Hamaminato
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Patent number: 8170149Abstract: An OFDM receiver apparatus receives an OFDM signal including a plurality of DBPSK signals transmitting identical information. An extraction unit extracts the plurality of DBPSK signals from the OFDM signal. A phase difference calculation unit calculates a phase difference between symbols of each of the plurality of extracted DBPSK signals. An accumulation unit accumulates the plurality of phase differences. A decision unit decides data transmitted by the DBPSK signals on the basis of an accumulation result.Type: GrantFiled: December 18, 2007Date of Patent: May 1, 2012Assignee: Fujitsu Semiconductor LimitedInventor: Naoto Adachi
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Patent number: 8149935Abstract: An FFT unit generates a frequency-domain signal for one-segment broadcasting and a frequency-domain signal for full-segment broadcasting. Under a good reception environment, the frequency-domain signal for the full-segment broadcasting is extracted by a switching control unit and the transmitted data for the full-segment broadcasting are recovered. When the reception environment deteriorates, both the one-segment broadcasting and the full-segment broadcasting are temporary demodulated. After a delay time due to the demodulation process has passed, a reception mode is switched from the full-segment broadcasting to the one-segment broadcasting.Type: GrantFiled: December 30, 2008Date of Patent: April 3, 2012Assignee: Fujitsu Semiconductor LimitedInventor: Naoto Adachi
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Patent number: 8135080Abstract: A receiver circuit in each branch has an FFT unit that performs Fourier transform on OFDM signals. A slave branch FFT window control unit determines whether an undesired wave is a preceding wave or a delay wave, and notifies a master branch of the result. In response to the notification from the slave branch, a master branch FFT window control unit controls a position of an FFT window that indicates a time range in which Fourier transform is performed on OFDM signals.Type: GrantFiled: July 29, 2008Date of Patent: March 13, 2012Assignee: Fujitsu Semiconductor LimitedInventors: Naoto Adachi, Makoto Hamaminato
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Patent number: 7912136Abstract: A receiver that receives a digital signal transmitted on the basis of an orthogonal frequency division multiplexing (OFDM) method. This receiver comprises a demodulation unit for demodulating the digital signal, a demapping unit for demapping demodulated data output from the demodulation unit, a frequency deinterleave unit for executing a frequency deinterleaving process on data output from the demapping unit, a delay unit for delaying control information superposed on the digital signal by a prescribed time period, and a time deinterleave unit for executing, on the basis of the interleave length specified by the control information delayed by the delay unit, a time deinterleaving process on data on which the frequency deinterleaving process has been executed.Type: GrantFiled: October 31, 2006Date of Patent: March 22, 2011Assignee: Fujitsu Semiconductor LimitedInventor: Naoto Adachi
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Publication number: 20110004806Abstract: A data receiving circuit includes: a first de-interleave circuit configured to de-interleave first data which is demodulated and is soft-decision-processed; a second de-interleave circuit configured to de-interleave second data which is demodulated and is soft-decision-processed; a memory configured to be shared by the first de-interleave circuit and the second de-interleave circuit and store respective hard decision information and respective soft decision information of the first data and the second data; and a memory control circuit configured to vary a first through fourth number of bits stored in the memory, the first number corresponding to the hard decision information of the first data, the second number corresponding to the soft decision information of the first data, the third number corresponding to the hard decision information of the second data, the fourth number corresponding to the soft decision information of the second data.Type: ApplicationFiled: July 2, 2010Publication date: January 6, 2011Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventor: Naoto ADACHI
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Patent number: 7864888Abstract: A transmission mode/guard length detection circuit that uses the Orthogonal Frequency Division Multiplexing method, in which: a difference between a reference wave having a constant period generated on the basis of a transmission mode length that is a time period length of the predetermined symbol and a guard length that is a time period length of the guard interval and the peak value interval is calculated as a shift amount, and the shift amount is integrated for a symbol and is output, and the result of the integration for a predetermined symbol is changed on the basis of the shift amount.Type: GrantFiled: November 30, 2007Date of Patent: January 4, 2011Assignee: Fujitsu Semiconductor LimitedInventor: Naoto Adachi
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Publication number: 20100303163Abstract: A demodulating circuit includes: a fast Fourier transform circuit which fast Fourier transforms a received signal and outputs a plurality of carrier signals; an output selecting circuit which selects at least two signals from the plurality of carrier signals, the at least two signals including a first signal modulated in accordance with a first modulation method and a second signal modulated in accordance with a second modulation method; an inverse fast Fourier transform circuit which inverse Fourier transforms transmission path characteristic values including a first transmission path characteristic value obtained based on the first signal and a second transmission path characteristic value obtained based on the second signal; and an FFT window control circuit which controls a position of an FFT window based on the inverse Fourier transformed transmission path characteristic values.Type: ApplicationFiled: May 18, 2010Publication date: December 2, 2010Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventor: Naoto ADACHI
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Patent number: 7835475Abstract: A tuner selects a channel in a designated frequency band. An FFT circuit converts a received signal in the selected channel into a plurality of carrier signals. A carrier shift detection circuit calculates the correlation between the phase information of each carrier signal and reference phase information prepared in advance. If the correlation is larger than a given threshold, it is determined that an OFDM signal is present in the search target channel. A TMCC extraction circuit analyzes the TMCC of the received signal and determines whether or not digital broadcasts of the search target channel can be received.Type: GrantFiled: October 26, 2006Date of Patent: November 16, 2010Assignee: Fujitsu Semiconductor LimitedInventor: Naoto Adachi
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Publication number: 20100172909Abstract: The objective to be solved by the present invention is to provide a method for effectively suppressing cerebral edema. The method for suppressing cerebral edema according to the present invention is characterized in comprising a step of administering an anti-HMGB 1 antibody recognizing 208EEEDDDDE215 (SEQ ID NO:1) as an HMGB1 epitope.Type: ApplicationFiled: January 4, 2010Publication date: July 8, 2010Inventors: Masahiro Nishibori, Shuji Mori, Hideo Takahashi, Yasuko Tomono, Naoto Adachi, Keyue Liu
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Publication number: 20100113544Abstract: An object of the present invention is to provide a cerebral infarction suppressant which is effective for brain tissue necrosis after long-time ischemia as in actual cerebral infarction and has fewer side effects. The cerebral infarction suppressant of the present invention is characterized in that histidine is contained and the cerebral infarction is attributed to long-time ischemia.Type: ApplicationFiled: September 1, 2005Publication date: May 6, 2010Applicant: Ehime UniversityInventors: Naoto Adachi, Keyue Liu, Tatsuru Arai
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Patent number: 7706479Abstract: A carrier interpolation unit (a digital filter) performs interpolation processing of SP signal in the frequency domain. An IFFT circuit converts a frequency-domain signal into a time-domain signal. A delay profile generation unit generates a delay profile based on an output of the IFFT circuit. The filter control unit controls a pass band of the digital filter in accordance with the delay profile. An FFT window control unit controls a position of a window to extract a calculation range of FFT in accordance with the delay profile. When delay time of multipath is larger than the guard interval, and when the reception power of the interference wave is larger than a threshold, the pass band of the digital filter is minimized.Type: GrantFiled: November 16, 2006Date of Patent: April 27, 2010Assignee: Fujitsu Microelectronics LimitedInventor: Naoto Adachi
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Publication number: 20090285318Abstract: An FFT unit generates a frequency-domain signal for one-segment broadcasting and a frequency-domain signal for full-segment broadcasting. Under a good reception environment, the frequency-domain signal for the full-segment broadcasting is extracted by a switching control unit and the transmitted data for the full-segment broadcasting are recovered. When the reception environment deteriorates, both the one-segment broadcasting and the full-segment broadcasting are temporary demodulated. After a delay time due to the demodulation process has passed, a reception mode is switched from the full-segment broadcasting to the one-segment broadcasting.Type: ApplicationFiled: December 30, 2008Publication date: November 19, 2009Applicant: FUJITSU MICROELECTRONICS LIMITEDInventor: Naoto ADACHI
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Publication number: 20090285086Abstract: An FFT unit generates a frequency domain signal by converting an OFDM signal using Fourier transform. A delay amount calculation unit generates a delay profile of the OFDM signal. The control determination unit detects a main wave and an interference wave using the delay profile. When the time difference between the main wave and a preceding wave is larger than a guard interval of the OFDM signal, an FFT window control unit sets the start position of the FFT window at a position shifted forward from the symbol start position of the main wave by an amount corresponding to the guard interval.Type: ApplicationFiled: December 30, 2008Publication date: November 19, 2009Applicant: FUJITSU MICROELECTRONICS LIMITEDInventor: Naoto ADACHI
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Publication number: 20090252739Abstract: An objective of the present invention is to provide a suppressant for cerebral infarction occurred after long-term ischemia associated with actual cerebral infarction, and has fewer side effects. The cerebral infarction suppressant of the present invention is characterized in comprising an anti-HMGB1 monoclonal antibody as an active ingredient.Type: ApplicationFiled: October 13, 2006Publication date: October 8, 2009Inventors: Masahiro Nishibori, Shuji Mori, Hideo Takahashi, Yasuko Tomono, Naoto Adachi, Keyue Liu
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Publication number: 20090097577Abstract: An OFDM signal is demodulated to generate a frequency domain signal in each of a plurality of branches. A diversity combining unit combines the demodulated signals respectively obtained in each of the branches. A clock recovery unit recovers the clock for the OFDM signal. A guard correlation unit detects the phase error of the OFDM signal. A decision unit identifies a branch having high reliability. A clock error correction unit generates a correction instruction, in accordance with the average value of the phase errors in the branch having high reliability. The clock recovery unit in each of the branches respectively corrects the error of the clock in accordance with the correction instruction.Type: ApplicationFiled: July 30, 2008Publication date: April 16, 2009Applicant: Fujitsu Microelectronics LimitedInventors: Naoto Adachi, Makoto Hamaminato
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Publication number: 20090097576Abstract: A receiver circuit in each branch has an FFT unit that performs Fourier transform on OFDM signals. A slave branch FFT window control unit determines whether an undesired wave is a preceding wave or a delay wave, and notifies a master branch of the result. In response to the notification from the slave branch, a master branch FFT window control unit controls a position of an FFT window that indicates a time range in which Fourier transform is performed on OFDM signals.Type: ApplicationFiled: July 29, 2008Publication date: April 16, 2009Applicant: FUJITSU MICROELCTRONICS LIMITEDInventors: Naoto ADACHI, Makoto Hamaminato