Patents by Inventor Navdeep S. Sooch
Navdeep S. Sooch has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6922469Abstract: A communication system of the present invention utilizes ring detection circuitry on both sides of an isolation barrier. More particularly, the ring detection circuitry may include ring burst circuitry on the phone line side of the isolation barrier and ringer timing circuits on the powered side of the isolation barrier. The digital burst peak signal may be transmitted through the isolation banier to the finger timing circuits. By splitting the ring detection circuitry so that the ringer timing circuits are placed on the powered side of the isolation barriers, a significant reduction in the power usage on the phone line side of the barrier related to the ring detection function may occur. The outputs of the ringing timing circuits may be provided to circuits on either side of the isolation barrier. Thus, the ring detection function may be accomplished in a system utilizing an efficient bidirectional capacitive barrier while still minimizing power usage on the line side of the barrier.Type: GrantFiled: May 5, 2003Date of Patent: July 26, 2005Assignee: Silicon Laboratories, Inc.Inventors: Jeffrey W. Scott, Navdeep S. Sooch, David R. Welland, Jerrell P. Hein
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Publication number: 20040247108Abstract: A digital direct access arrangement (DAA) circuitry may be used to terminate the telephone connections at the user's end to provide a communication path for signals to and from the phone lines. Briefly described, a means for providing a proper hookswitch transition for a variety of international phone standards is provided. The invention may also be utilized with means for transmitting and receiving a signal across a capacitive isolation barrier. More particularly, a DAA circuitry may be utilized which satisfies many or all hookswitch transition standards without the use of additional discrete devices. The hookswitch transition standards may be satisfied by ramping down the current flowing through the hookswitch prior to transitioning the hookswitch state. In this manner the hookswitch current change as a function of time (di/dt) may be decreased. Thus, the current through the hookswitch may be actively controlled prior to switching the hookswitch from an off-hook condition to an on-hook condition.Type: ApplicationFiled: June 29, 2004Publication date: December 9, 2004Applicant: Silicon Laboratories Inc.Inventors: George Tyson Tuttle, Jeffrey W. Scott, Navdeep S. Sooch, David R. Welland
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Patent number: 6823066Abstract: A digital direct access arrangement (DAA) circuitry may be used to terminate the telephone connections at the user's end to provide a communication path for signals to and from the phone lines. Briefly described, a means for providing a proper hookswitch transition for a variety of international phone standards is provided. The invention may also be utilized with means for transmitting and receiving a signal across a capacitive isolation barrier. More particularly, a DAA circuitry may be utilized which satisfies many or all hookswitch transition standards without the use of additional discrete devices. The hookswitch transition standards may be satisfied by ramping down the current flowing through the hookswitch prior to transitioning the hookswitch state. In this manner the hookswitch current change as a function of time (di/dt) may be decreased. Thus, the current through the hookswitch may be actively controlled prior to switching the hookswitch from an off-hook condition to an on-hook condition.Type: GrantFiled: July 2, 1999Date of Patent: November 23, 2004Assignee: Silicon Laboratories Inc.Inventors: George Tyson Tuttle, Jeffrey W. Scott, Navdeep S. Sooch, David R. Welland
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Publication number: 20040228475Abstract: A CMOS implementation for a DC holding circuit in direct access arrangement (DAA) circuitry is disclosed that provides desirable inductive behavior while minimizing power dissipation required by the CMOS integrated circuit, particularly at high loop currents. The DC holding circuitry disclosed may include MOS transistors located on a CMOS integrated circuit and an off-chip power dissipating resistor that acts to dissipate power external to the CMOS integrated circuit. The CMOS implementation disclosed also allows a path for drawing DC current to power other CMOS circuits (e.g., ADCs and DACs) in the CMOS integrated circuit.Type: ApplicationFiled: June 15, 2004Publication date: November 18, 2004Applicant: Silicon Laboratories Inc.Inventors: Jeffrey W. Scott, Navdeep S. Sooch, David R. Welland
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Publication number: 20040190670Abstract: A digital direct access arrangement (DAA) circuitry may be used to terminate the telephone connections at the user's end that provides a communication path for signals to and from the phone lines. Briefly described, the DAA provides a programmable means for the DC termination for a variety of international phone standards. The invention may also be utilized with means for transmitting and receiving a signal across a capacitive isolation barrier. More particularly, a DC holding circuit is provided in which a programmable DC current limiting mode is available. In the current limiting mode, power may be dissipated in devices external to a DAA integrated circuit. Moreover, much of the power may be dissipated in external passive devices, such as resistors.Type: ApplicationFiled: October 3, 2003Publication date: September 30, 2004Applicant: Silicon Laboratories Inc.Inventors: Timothy J. Dupuis, George Tyson Tuttle, Jeffrey W. Scott, Navdeep S. Sooch, David R. Welland
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Publication number: 20040161023Abstract: An isolation system is provided that is suitable for use in telephony, medical instrumentation, industrial process control and other applications. Preferred embodiments of the invention comprise a capacitive isolation barrier across which a digital signal is communicated. The system provides a means of communication across the isolation barrier that is highly immune to amplitude and phase noise interference. Clock recovery circuitry may be employed on one side of the isolation barrier to extract timing information from the digital signal communicated across the barrier, and to filter the effects of phase noise introduced at the barrier. Delta-sigma converters may be disposed on both sides of the isolation barrier to convert signals between analog and digital domains. An isolated power supply may also be provided on the isolated side of the barrier, whereby direct current is generated in response to the digital data received across the isolation barrier.Type: ApplicationFiled: February 17, 2004Publication date: August 19, 2004Applicant: Silicon Laboratories, Inc.Inventors: Jeffrey W. Scott, Navdeep S. Sooch, David R. Welland
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Publication number: 20040161024Abstract: An isolation system is provided that is suitable for use in telephony, medical instrumentation, industrial process control and other applications. Preferred embodiments of the invention comprise a capacitive isolation barrier across which a digital signal is communicated. The system provides a means of communication across the isolation barrier that is highly immune to amplitude and phase noise interference. Clock recovery circuitry may be employed on one side of the isolation barrier to extract timing information from the digital signal communicated across the barrier, and to filter the effects of phase noise introduced at the barrier. Delta-sigma converters may be disposed on both sides of the isolation barrier to convert signals between analog and digital domains. An isolated power supply may also be provided on the isolated side of the barrier, whereby direct current is generated in response to the digital data received across the isolation barrier.Type: ApplicationFiled: February 17, 2004Publication date: August 19, 2004Applicant: Silicon Laboratories, Inc.Inventors: Jeffrey W. Scott, Navdeep S. Sooch, David R. Welland
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Patent number: 6754341Abstract: A CMOS implementation for a DC holding circuit in direct access arrangement (DAA) circuitry is disclosed that provides desirable inductive behavior while minimizing power dissipation required by the CMOS integrated circuit, particularly at high loop currents. The DC holding circuitry disclosed may include MOS transistors located on a CMOS integrated circuit and an off-chip power dissipating resistor that acts to dissipate power external to the CMOS integrated circuit. The CMOS implementation disclosed also allows a path for drawing DC current to power other CMOS circuits (e.g. ADCs and DACs) in the CMOS integrated circuit.Type: GrantFiled: October 9, 2001Date of Patent: June 22, 2004Assignee: Silicon Laboratories, Inc.Inventors: Jeffrey W. Scott, Navdeep S. Sooch, David R. Welland
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Publication number: 20040101132Abstract: An isolation system is provided that is suitable for use in telephony, medical instrumentation, industrial process control and other applications. Preferred embodiments of the invention comprise a capacitive isolation barrier across which a digital signal is communicated. The system provides a means of communication across the isolation barrier that is highly immune to amplitude and phase noise interference. Clock recovery circuitry may be employed on one side of the isolation barrier to extract timing information from the digital signal communicated across the barrier, and to filter the effects of phase noise introduced at the barrier. Delta-sigma converters may be disposed on both sides of the isolation barrier to convert signals between analog and digital domains. An isolated power supply may also be provided on the isolated side of the barrier, whereby direct current is generated in response to the digital data received across the isolation barrier.Type: ApplicationFiled: November 18, 2003Publication date: May 27, 2004Applicant: Silicon Laboratories Inc.Inventors: Jeffrey W. Scott, Navdeep S. Sooch, David R. Welland
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Publication number: 20040096006Abstract: An isolation system is provided that is suitable for use in telephony, medical instrumentation, industrial process control and other applications. Preferred embodiments of the invention comprise a capacitive isolation barrier across which a digital signal is communicated. The system provides a means of communication across the isolation barrier that is highly immune to amplitude and phase noise interference. Clock recovery circuitry may be employed on one side of the isolation barrier to extract timing information from the digital signal communicated across the barrier, and to filter the effects of phase noise introduced at the barrier. Delta-sigma converters may be disposed on both sides of the isolation barrier to convert signals between analog and digital domains. An isolated power supply may also be provided on the isolated side of the barrier, whereby direct current is generated in response to the digital data received across the isolation barrier.Type: ApplicationFiled: June 25, 2003Publication date: May 20, 2004Applicant: Silicon Laboratories Inc.Inventors: Jeffrey W. Scott, Navdeep S. Sooch, David R. Welland
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Publication number: 20040091100Abstract: A CMOS implementation for a DC holding circuit in direct access arrangement (DAA) circuitry is disclosed that provides desirable inductive behavior while minimizing power dissipation required by the CMOS integrated circuit, particularly at high loop currents. The DC holding circuitry disclosed may include MOS transistors located on a CMOS integrated circuit and an off-chip power dissipating resistor that acts to dissipate power external to the CMOS integrated circuit. The CMOS implementation disclosed also allows a path for drawing DC current to power other CMOS circuits (e.g., ADCs and DACs) in the CMOS integrated circuit.Type: ApplicationFiled: June 30, 2003Publication date: May 13, 2004Applicant: Silicon Laboratories Inc.Inventors: Jeffrey W. Scott, Andrew W. Krone, Navdeep S. Sooch, David R. Welland
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Publication number: 20040081232Abstract: An isolation system is provided that is suitable for use in telephony, medical instrumentation, industrial process control and other applications. Preferred embodiments of the invention comprise a capacitive isolation barrier across which a digital signal is communicated. The system provides a means of communication across the isolation barrier that is highly immune to amplitude and phase noise interference. Clock recovery circuitry may be employed on one side of the isolation barrier to extract timing information from the digital signal communicated across the barrier, and to filter the effects of phase noise introduced at the barrier. Delta-sigma converters may be disposed on both sides of the isolation barrier to convert signals between analog and digital domains. An isolated power supply may also be provided on the isolated side of the barrier, whereby direct current is generated in response to the digital data received across the isolation barrier.Type: ApplicationFiled: June 23, 2003Publication date: April 29, 2004Applicant: Silicon Laboratories Inc.Inventors: Jeffrey W. Scott, Navdeep S. Sooch, David R. Welland
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Publication number: 20040057524Abstract: An improved digital capacitive isolation barrier system is provided that is suitable for use in a telephone or modem where the locally powered circuits must be effectively isolated from the public telephone system, while permitting data transfer across the barrier. In particular, an automatic ADC offset calibration system is provided for determining the magnitude of the ADC offset signal required in the system during a calibration operation, and for providing the calibrated ADC offset signal during normal operation of the isolation barrier system. A modified hybrid circuit is provided for isolating the system input from the telephone line during calibration, and for completing the calibration loop. Fixed bias signals are also provided for the ADC and for a DAC in the system. In a preferred embodiment, the ADC is located on the isolated side of the isolation barrier, while the integrator and register that determine and hold the offset signal are located on the powered side of the isolation barrier.Type: ApplicationFiled: September 26, 2003Publication date: March 25, 2004Applicant: Silicon Laboratories Inc.Inventors: Andrew W. Krone, Timothy J. Dupuis, Jeffrey W. Scott, Navdeep S. Sooch, David R. Welland
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Patent number: 6683548Abstract: An isolation system is provided that is suitable for use in telephony, medical instrumentation, industrial process control and other applications. Preferred embodiments of the invention comprise a capacitive isolation barrier across which a digital signal is communicated. The system provides a means of communication across the isolation barrier that is highly immune to amplitude and phase noise interference. Clock recovery circuitry may be employed on one side of the isolation barrier to extract timing information from the digital signal communicated across the barrier, and to filter the effects of phase noise introduced at the barrier. Delta-sigma converters may be disposed on both sides of the isolation barrier to convert signals between analog and digital domains. An isolated power supply may also be provided on the isolated side of the barrier, whereby direct current is generated in response to the digital data received across the isolation barrier.Type: GrantFiled: January 17, 2003Date of Patent: January 27, 2004Assignee: Silicon Laboratories Inc.Inventors: Jeffrey W. Scott, Navdeep S. Sooch, David R. Welland
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Patent number: 6654409Abstract: An isolation system for terminating a phone line is provided. The invention may comprise a capacitive isolation barrier across which a digital signal is communicated. Clock recovery circuitry may be employed on one side of the isolation barrier to extract timing information from the digital signal communicated across the barrier. An isolated power supply may also be provided on the isolated side of the barrier, whereby direct current is generated in response to the digital data received across the isolation barrier. A bidirectional isolation system is provided whereby bidirectional communication of digital signals is accomplished using a single pair of isolation capacitors. In preferred embodiments, the digital data communicated across the barrier consists of digital delta-sigma data signals multiplexed in time with other digital control, signaling and framing information.Type: GrantFiled: December 22, 1999Date of Patent: November 25, 2003Assignee: Silicon Laboratories, Inc.Inventors: Jeffrey W. Scott, Navdeep S. Sooch, David R. Welland
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Publication number: 20030206626Abstract: A communication system is provided with a power supply budget such that portions of a phone line side circuit may be powered from the TIP and RING phone lines while using standard electronic devices for the hookswitch circuits and the diode bridge circuit. For example, low voltage converters in the phone line side circuit may be powered from the phone line. The low voltage converters may operate off a low voltage power supply of approximately 2.5 V or less, more preferably may operate off a low voltage power supply of approximately 2.0 V or less, and in one embodiment 1.9 V converters may be utilized. The communication system may further include a capacitive isolation barrier system for isolating the phone line side circuitry.Type: ApplicationFiled: May 5, 2003Publication date: November 6, 2003Inventors: Jeffrey W. Scott, Navdeep S. Sooch, David R. Welland, Jerrell P. Hein, Andrew W. Krone
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Publication number: 20030194083Abstract: A communication system is provided with a power supply budget such that portions of a phone line side circuit may be powered from the TIP and RING phone lines while using standard electronic devices for the hookswitch circuits and the diode bridge circuit. For example, low voltage converters in the phone line side circuit may be powered from the phone line. The low voltage converters may operate off a low voltage power supply of approximately 2.5 V or less, more preferably may operate off a low voltage power supply of approximately 2.0 V or less, and in one embodiment 1.9 V converters may be utilized. The communication system may further include a capacitive isolation barrier system for isolating the phone line side circuitry.Type: ApplicationFiled: May 5, 2003Publication date: October 16, 2003Inventors: Jeffrey W. Scott, Navdeep S. Sooch, David R. Welland, Jerrell P. Hein
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Patent number: 6611553Abstract: An isolation system is provided that is suitable for use in telephony, medical instrumentation, industrial process control and other applications. Preferred embodiments of the invention comprise a capacitive isolation barrier across which a digital signal is communicated. The system provides a means of communication across the isolation barrier that is highly immune to amplitude and phase noise interference. Clock recovery circuitry may be employed on one side of the isolation barrier to extract timing information from the digital signal communicated across the barrier, and to filter the effects of phase noise introduced at the barrier. Delta-sigma converters may be disposed on both sides of the isolation barrier to convert signals between analog and digital domains. An isolated power supply may also be provided on the isolated side of the barrier, whereby direct current is generated in response to the digital data received across the isolation barrier.Type: GrantFiled: June 9, 2000Date of Patent: August 26, 2003Assignee: Silicon Laboratories Inc.Inventors: Jeffrey W. Scott, Navdeep S. Sooch, David R. Welland
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Patent number: 6587560Abstract: A communication system is provided with a power supply budget such that portions of a phone line side circuit are powered from the TIP and RING phone lines while using standard electronic devices for the hookswitch circuits and the diode bridge circuit. For example, low voltage converters in the phone line side circuit are powered from the phone line. The low voltage converters operate off a low voltage power supply of approximately 2.5 V or less, more preferably operate off a low voltage power supply of approximately 2.0 V or less, and in one embodiment 1.9 V converters are utilized. In one embodiment, the communication system further includes a capacitive isolation barrier system for isolating the phone line side circuitry.Type: GrantFiled: March 4, 1998Date of Patent: July 1, 2003Assignee: Silicon Laboratories Inc.Inventors: Jeffrey W. Scott, Navdeep S. Sooch, David R. Welland
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Publication number: 20030107505Abstract: An isolation system is provided that is suitable for use in telephony, medical instrumentation, industrial process control and other applications. Preferred embodiments of the invention comprise a capacitive isolation barrier across which a digital signal is communicated. The system provides a means of communication across the isolation barrier that is highly immune to amplitude and phase noise interference. Clock recovery circuitry may be employed on one side of the isolation barrier to extract timing information from the digital signal communicated across the barrier, and to filter the effects of phase noise introduced at the barrier. Delta-sigma converters may be disposed on both sides of the isolation barrier to convert signals between analog and digital domains. An isolated power supply may also be provided on the isolated side of the barrier, whereby direct current is generated in response to the digital data received across the isolation barrier.Type: ApplicationFiled: January 17, 2003Publication date: June 12, 2003Applicant: Silicon Laboratories, Inc.Inventors: Jeffrey W. Scott, Navdeep S. Sooch, David R. Welland