Abstract: A CMOS implementation for a DC holding circuit in direct access arrangement (DAA) circuitry is disclosed that provides desirable inductive behavior while minimizing power dissipation required by the CMOS integrated circuit, particularly at high loop currents. The DC holding circuitry disclosed may include MOS transistors located on a CMOS integrated circuit and an off-chip power dissipating resistor that acts to dissipate power external to the CMOS integrated circuit. The CMOS implementation disclosed also allows a path for drawing DC current to power other CMOS circuits (e.g. ADCs and DACs) in the CMOS integrated circuit.

Abstract: A CMOS implementation for a DC holding circuit in direct access arrangement (DAA) circuitry is disclosed that provides desirable inductive behavior while minimizing power dissipation required by the CMOS integrated circuit, particularly at high loop currents. The DC holding circuitry disclosed may include MOS transistors located on a CMOS integrated circuit and an off-chip power dissipating resistor that acts to dissipate power external to the CMOS integrated circuit. The CMOS implementation disclosed also allows a path for drawing DC current to power other CMOS circuits (e.g. ADCs and DACs) in the CMOS integrated circuit.

Abstract: A digital capacitive isolation barrier system is provided that is suitable for use in a telephone or modem where the locally powered circuits must be effectively isolated from the public telephone system, while permitting data transfer across the barrier. In particular, an automatic ADC offset calibration system is provided for determining the magnitude of the ADC offset signal required in the system during a calibration operation, and for providing the ADC offset signal during normal operation of the isolation barrier system. Fixed bias signals are also provided for the ADC and for a DAC in the system. In a preferred embodiment, the ADC is located on the isolated side of the isolation barrier, while the integrator and register that determine and hold the offset signal are located on the powered side of the isolation barrier.

Abstract: A method and apparatus are provided for suspending or freezing outputs from an isolation barrier system, which may be a digital capacitive isolation barrier system, during the occurrence of events that may disrupt proper operation of the system. Examples of such disruptive events are data rate changes during modem baud rate negotiations, transition to low-power mode, and going off-hook in a telephony system. In each of these cases, the master circuit anticipates the disruption and sends a freeze signal to the isolated circuit. The freeze signal instructs the isolated circuit to enter freeze mode, and no data is sent through the isolation system. Internal control signals are generated and used to establish synchronization and framing after the disruption, and to restore normal operation of the isolation system. In preferred embodiments, the duration of the freeze period may be determined by a timer or by circuitry that detects framing lock or the presence of transients in the system.

Abstract: An isolation system is provided that is suitable for use in telephony, medical instrumentation, industrial process control and other applications. Preferred embodiments of the invention comprise a capacitive isolation barrier across which a digital signal is communicated. The system provides a means of communication across the isolation barrier that is highly immune to amplitude and phase noise interference. Clock recovery circuitry may be employed on one side of the isolation barrier to extract timing information from the digital signal communicated across the barrier, and to filter the effects of phase noise introduced at the barrier. Delta-sigma converters may be disposed on both sides of the isolation barrier to convert signals between analog and digital domains. An isolated power supply may also be provided on the isolated side of the barrier, whereby direct current is generated in response to the digital data received across the isolation barrier.

Abstract: A capacitive interface may be utilized to provide a linear output from the TIP and RING phone lines to ringer circuitry. Because the interface provides a linear signal, the input provided to the ringer circuitry may also be utilized for other functions in addition to ringer detection functions. More particularly, the outputs of the capacitive interface may also be connected to caller ID circuitry input lines so as to also provide caller ID data. The use of common inputs for the ringer circuitry and the caller ID circuitry eliminates the need for a separate caller ID interface.

Abstract: A digital capacitive isolation barrier system is provided that is suitable for use in a telephone or modem where the locally powered circuits must be effectively isolated from the public telephone system, while permitting data transfer across the barrier. In particular, an automatic ADC offset calibration system is provided for determining the magnitude of the ADC offset signal required in the system during a calibration operation, and for providing the ADC offset signal during normal operation of the isolation barrier system. The offset calibration system includes a coarse offset signal generator which provides ;elected increments of offset voltage to the ADC outside of the outgoing data signal channel, In order to increase the calibration range and to avoid injecting large offset voltages into the outgoing data channel. Fixed bias signals are also provided for the ADC and for a DAC in the system.

Abstract: An isolation system is provided that is suitable for use in telephony, medical instrumentation, industrial process control and other applications. Preferred embodiments of the invention comprise a capacitive isolation barrier across which a digital signal is communicated. The system provides a means of communication across the isolation barrier that is highly immune to amplitude and phase noise interference. Clock recovery circuitry may be employed on one side of the isolation barrier to extract timing information from the digital signal communicated across the barrier, and to filter the effects of phase noise introduced at the barrier. Delta-sigma converters may be disposed on both sides of the isolation barrier to convert signals between analog and digital domains. An isolated power supply may also be provided on the isolated side of the barrier, whereby direct current is generated in response to the digital data received across the isolation barrier.

Abstract: A CMOS implementation for a DC holding circuit in direct access arrangement (DAA) circuitry is disclosed that provides desirable inductive behavior while minimizing power dissipation required by the CMOS integrated circuit, particularly at high loop currents. The DC holding circuitry disclosed may include MOS transistors located on a CMOS integrated circuit and an off-chip power dissipating resistor that acts to dissipate power external to the CMOS integrated circuit. The CMOS implementation disclosed also allows a path for drawing DC current to power other CMOS circuits (e.g., ADCs and DACs) in the CMOS integrated circuit.

Abstract: An isolation system is provided that is suitable for use in telephony, medical instrumentation, industrial process control and other applications. Preferred embodiments of the invention comprise a capacitive isolation barrier across which a digital signal is communicated. The system provides a means of communication across the isolation barrier that is highly immune to amplitude and phase noise interference. Clock recovery circuitry may be employed on one side of the isolation barrier to extract timing information from the digital signal communicated across the barrier, and to filter the effects of phase noise introduced at the barrier. Delta-sigma converters may be disposed on both sides of the isolation barrier to convert signals between analog and digital domains. An isolated power supply may also be provided on the isolated side of the barrier, whereby direct current is generated in response to the digital data received across the isolation barrier.

Abstract: Monitor circuitry is disclosed that produces a loop current monitor signal indicative of the DC loop current passing through DC holding circuitry, which may be part of phone line side circuitry that may be connected to phone lines. This loop current monitor signal may be digitized and then communicated across an isolation barrier to powered side circuitry as digital information representative of the DC loop current levels in the phone lines. Example embodiments for the monitor circuitry are also disclosed, such as a MOS transistor, for which the monitor signal is the drain current of the MOS transistor, and an external resistor, for which the monitor signal is a voltage associated with the external resistor.

Abstract: A digital direct access arrangement (DAA) circuitry may be used to terminate the telephone connections at the user's end that provides a communication path for signals to and from the phone lines. Briefly described, the DAA provides a programmable means for the DC termination for a variety of international phone standards. The invention may also be utilized with means for transmitting and receiving a signal across a capacitive isolation barrier. More particularly, a DC holding circuit is provided that has switchable time constants. A first time constant may be utilized during a first operation phase immediately after off-hook conditions to allow for fast settling times. Then, a second operation phase is entered in which a second time constant may be utilized. During the second operation phase the DC holding circuit operates slower to create improved low frequency performance.

Abstract: A communication system is provided with a capacitive isolation barrier in which at least a portion of the ring detection circuits may be integrated into the line side circuitry. Moreover the ring detection circuits on the phone line side of the isolation barrier may be powered at least in part by power transmitted from the powered side of the isolation barrier to the phone line side of the isolation barrier through the barrier capacitors. A capacitive interface may directly connect the ringer circuitry on the phone line side of the barrier to the TIP/RING lines. The capacitive interface operates to linearly attenuate the TIP/RING signal voltage levels from the high phone line levels to levels within integrated circuit technology limitations.

Abstract: An isolation system is provided that is suitable for use in telephony, medical instrumentation, industrial process control and other applications. Preferred embodiments of the invention comprise a capacitive isolation barrier across which a digital signal is communicated. The system provides a means of communication across the isolation barrier that is highly immune to amplitude and phase noise interference. Clock recovery circuitry may be employed on one side of the isolation barrier to extract timing information from the digital signal communicated across the barrier, and to filter the effects of phase noise introduced at the barrier. Delta-sigma converters may be disposed on both sides of the isolation barrier to convert signals between analog and digital domains. An isolated power supply may also be provided on the isolated side of the barrier, whereby direct current is generated in response to the digital data received across the isolation barrier.

Abstract: A CMOS implementation for a DC holding circuit in direct access arrangement (DAA) circuitry is disclosed that provides desirable inductive behavior while minimizing power dissipation required by the CMOS integrated circuit, particularly at high loop currents. The DC holding circuitry disclosed may include MOS transistors located on a CMOS integrated circuit and an off-chip power dissipating resistor that acts to dissipate power external to the CMOS integrated circuit. The CMOS implementation disclosed also allows a path for drawing DC current to power other CMOS circuits (e.g., ADCs and DACs) in the CMOS integrated circuit.

Abstract: An analog successive approximation (SAR) analog-to-digital converter (ADC) is disclosed that is a compromise between a SAR ADC implementation and a fully parallel thermometer-to-binary ADC. The analog SAR ADC utilizes N comparators for N bits of output and does not require a clock system, control logic, decode logic, or thermometer-to-binary decode circuitry. Conversion speed is determined by the comparator rate, and the comparator outputs may be used directly as the ADC outputs. The analog SAR ADC disclosed is a low complexity, low-precision analog-to-digital converter (ADC) that may be used to digitize phone line status information so that it may be communicated across a isolation barrier as digital information.

Abstract: The communication system disclosed herein allows for the hookswitch devices to draw loop current from the phone line in both on-hook and off-hook conditions. Thus, even though an on-hook condition occurs, current may be obtained through the hookswitch devices. This feature allows circuitry which operates during on-hook conditions to still receive power from the phone line. Moreover because the hookswitch devices are utilized for drawing power in both on-hook and off-hook conditions, the use of additional switches dedicated to drawing the power during on-hook conditions is not required. For example, loop current may be drawn from the phone line through the hookswitch devices to power circuits used to perform the on-hook caller ID function. The powered circuits may include for example analog to digital converters. The technique disclosed herein for drawing current through the hookswitch devices is particularly useful for communications systems which utilize a capacitive isolation barrier system.

Abstract: A digital capacitive isolation barrier system is provided that is suitable for use in a telephone or modem where the locally powered circuits must be effectively isolated from the public telephone system, while permitting data transfer across the barrier. In particular, an automatic ADC offset calibration system is provided for determining the magnitude of the ADC offset signal required in the system during a calibration operation, and for providing the ADC offset signal during normal operation of the isolation barrier system. Fixed bias signals are also provided for the ADC and for a DAC in the system. In a preferred embodiment, the ADC is located on the isolated side of the isolation barrier, while the integrator and register that determine and hold the offset signal are located on the powered side of the isolation barrier.

Abstract: An isolation system is provided that is suitable for use in telephony, medical instrumentation, industrial process control and other applications. Preferred embodiments of the invention comprise a capacitive isolation barrier across which a digital signal is communicated. The system provides a means of communication across the isolation barrier that is highly immune to amplitude and phase noise interference. Clock recovery circuitry may be employed on one side of the isolation barrier to extract timing information from the digital signal communicated across the barrier, and to filter the effects of phase noise introduced at the barrier. Delta-sigma converters may be disposed on both sides of the isolation barrier to convert signals between analog and digital domains. An isolated power supply may also be provided on the isolated side of the barrier, whereby direct current is generated in response to the digital data received across the isolation barrier.

Abstract: As isolation system is provided that is suitable for use in telephony, medical instrumentation, industrial process control and other applications. Preferred embodiments of the invention comprise a capacitive isolation barrier across which a digital signal is communicated. The system provides a means of communication across the isolation barrier that is highly immune to amplitude and phase noise interference. Clock recovery circuitry may be employed on one side of the isolation barrier to extract timing information from the digital signal communicated across the barrier, and to filter the effects of phase noise introduced at the barrier. Delta-sigma converters may be disposed on both sides of the isolation barrier to convert signals between analog and digital domains. An isolated power supply may also be provided on the isolated side of the barrier, whereby direct current is generated in response to the digital data received across the isolation barrier.