Patents by Inventor Navdeep S. Sooch

Navdeep S. Sooch has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6570513
    Abstract: An isolation system is provided that is suitable for use in telephony, medical instrumentation, industrial process control and other applications. Preferred embodiments of the invention comprise a capacitive isolation barrier across which a digital signal is communicated. The system provides a means of communication across the isolation barrier that is highly immune to amplitude and phase noise interference. Clock recovery circuitry may be employed on one side of the isolation barrier to extract timing information from the digital signal communicated across the barrier, and to filter the effects of phase noise introduced at the barrier. Delta-sigma converters may be disposed on both sides of the isolation barrier to convert signals between analog and digital domains. An isolated power supply may also be provided on the isolated side of the barrier, whereby direct current is generated in response to the digital data received across the isolation barrier.
    Type: Grant
    Filed: August 27, 2001
    Date of Patent: May 27, 2003
    Assignee: Silicon Laboratories Inc.
    Inventors: Jeffrey W. Scott, Navdeep S. Sooch, David R. Welland
  • Publication number: 20030091140
    Abstract: A digital direct access arrangement (DAA) circuitry may be used to terminate the telephone connections at the user's end that provides a communication path for signals to and from the phone lines. Briefly described, the DAA provides a programmable means for the DC termination for a variety of international phone standards. The invention may also be utilized with means for transmitting and receiving a signal across a capacitive isolation barrier. More particularly, a DC holding circuit is provided in which a programmable DC current limiting mode is available. In the current limiting mode, power may be dissipated in devices external to a DAA integrated circuit. Moreover, much of the power may be dissipated in external passive devices, such as resistors.
    Type: Application
    Filed: November 12, 2002
    Publication date: May 15, 2003
    Applicant: Silicon Laboratories Inc.
    Inventors: Timothy J. Dupuis, George Tyson Tuttle, Jeffrey W. Scott, Navdeep S. Sooch, David R. Welland
  • Patent number: 6522745
    Abstract: A digital direct access arrangement (DAA) circuitry may be used to terminate the telephone connections at the user's end to provide a communication path for signals to and from the phone lines. Briefly described, a means for providing a proper ringer impedance for a variety of international phone standards while also providing a proper isolation barrier to the phone line is disclosed. More particularly, a DAA circuitry may be utilized which satisfies many or all ringer impedance standards without the use of additional discrete impedance devices. The ringer impedance standards may be satisfied by use of an impedance structure coupled between the TIP and RING lines and actively controlling the current drawn through the hookswitch devices when a ringing event is detected so as to control the impedance seen at the TIP and RING lines during a ringing event. The detection of the ringing event may be performed on the phone line side of an isolation barrier.
    Type: Grant
    Filed: July 2, 1999
    Date of Patent: February 18, 2003
    Assignee: Silicon Laboratories Inc.
    Inventors: George Tyson Tuttle, Jeffrey W. Scott, Navdeep S. Sooch, David R. Welland
  • Patent number: 6516024
    Abstract: A digital direct access arrangement (DAA) circuitry may be used to terminate the telephone connections at the user's end that provides a communication path for signals to and from the phone lines. Briefly described, the DAA provides a programmable means for the DC termination for a variety of international phone standards. The invention may also be utilized with means for transmitting and receiving a signal across a capacitive isolation barrier. More particularly, a DC holding circuit is provided in which a programmable DC current limiting mode is available. In the current limiting mode, power may be dissipated in devices external to a DAA integrated circuit. Moreover, much of the power may be dissipated in external passive devices, such as resistors. Further, the current limiting mode includes a distortion adjustment circuit to limit distortion at a crossover point at which current limiting effects occur.
    Type: Grant
    Filed: June 16, 1998
    Date of Patent: February 4, 2003
    Assignee: Silicon Laboratories Inc.
    Inventors: Timothy J. Dupuis, George Tyson Tuttle, Jeffrey W. Scott, Navdeep S. Sooch, David R. Welland
  • Patent number: 6504864
    Abstract: A digital direct access arrangement (DAA) circuitry may be used to terminate the telephone connections at the user's end that provides a communication path for signals to and from the phone lines. Briefly described, the DAA provides a programmable means for the DC termination for a variety of international phone standards. The invention may also be utilized with means for transmitting and receiving a signal across a capacitive isolation barrier. More particularly, a DC holding circuit is provided that is a second order circuit. The use of a second order circuit provides improved distortion characteristics, particularly at low frequencies.
    Type: Grant
    Filed: June 16, 1998
    Date of Patent: January 7, 2003
    Assignee: Silicon Laboratories Inc.
    Inventors: Timothy J. Dupuis, George Tyson Tuttle, Jeffrey W. Scott, Navdeep S. Sooch, David R. Welland
  • Publication number: 20030002571
    Abstract: An isolation system is provided that is suitable for use in telephony, medical instrumentation, industrial process control and other applications. Preferred embodiments of the invention comprise a capacitive isolation barrier across which a digital signal is communicated. The system provides a means of communication across the isolation barrier that is highly immune to amplitude and phase noise interference. Clock recovery circuitry may be employed on one side of the isolation barrier to extract timing information from the digital signal communicated across the barrier, and to filter the effects of phase noise introduced at the barrier. Delta-sigma converters may be disposed on both sides of the isolation barrier to convert signals between analog and digital domains. An isolated power supply may also be provided on the isolated side of the barrier, whereby direct current is generated in response to the digital data received across the isolation barrier.
    Type: Application
    Filed: August 23, 2002
    Publication date: January 2, 2003
    Applicant: Silicon Laboratories Inc.
    Inventors: Jeffrey W. Scott, Navdeep S. Sooch, David R. Welland
  • Patent number: 6498825
    Abstract: A digital direct access arrangement (DAA) circuitry may be used to terminate the telephone connections at the user's end that provides a communication path for signals to and from the phone lines. Briefly described, the DAA provides a programmable means for the DC termination for a variety of international phone standards. The invention may also be utilized with means for transmitting and receiving a signal across a capacitive isolation barrier. More particularly, a DC holding circuit is provided in which a programmable DC current limiting mode is available. In the current limiting mode, power may be dissipated in devices external to a DAA integrated circuit. Moreover, much of the power may be dissipated in external passive devices, such as resistors.
    Type: Grant
    Filed: June 16, 1998
    Date of Patent: December 24, 2002
    Assignee: Silicon Laboratories Inc.
    Inventors: Timothy J. Dupuis, George Tyson Tuttle, Jeffrey W. Scott, Navdeep S. Sooch, David R. Welland
  • Patent number: 6480602
    Abstract: Ring-detect interface circuit is disclosed for digital DAA circuitry to provide a plurality of selectable signals, including a ring monitor signal, on a ring-detect output pin. The interface circuitry allows the digital DAA circuitry to interface with advanced controllers, such as advanced DSPs, while still being compatible with older controllers that expect only a ring monitor signal on the ring-detect pin. The interface circuitry may include a multiplexer that receives multiple status bits or signals, including the ring monitor signal, and that has its output controlled by a multiple-bit control register. In addition, the ring monitor signal may be communicated as a digital signal across an isolation barrier from phone line side circuitry to powered side circuitry and ultimately made available on the ring-detect output pin. Corresponding methods for improving compatibility of digital DAA circuitry through the ring-detect interface circuit are also disclosed.
    Type: Grant
    Filed: March 4, 1998
    Date of Patent: November 12, 2002
    Assignee: Silicon Laboratories, Inc.
    Inventors: Timothy J. Dupuis, Bradley J. Fluke, Jeffrey W. Scott, Navdeep S. Sooch, David R. Welland
  • Publication number: 20020154702
    Abstract: An isolation system is provided that is suitable for use in telephony, medical instrumentation, industrial process control and other applications. Preferred embodiments of the invention comprise a capacitive isolation barrier across which a digital signal is communicated. The system provides a means of communication across the isolation barrier that is highly immune to amplitude and phase noise interference. Clock recovery circuitry may be employed on one side of the isolation barrier to extract timing information from the digital signal communicated across the barrier, and to filter the effects of phase noise introduced at the barrier. Delta-sigma converters may be disposed on both sides of the isolation barrier to convert signals between analog and digital domains. An isolated power supply may also be provided on the isolated side of the barrier, whereby direct current is generated in response to the digital data received across the isolation barrier.
    Type: Application
    Filed: April 22, 2002
    Publication date: October 24, 2002
    Applicant: Silicon Laboratories Inc.
    Inventors: Jeffrey W. Scott, Navdeep S. Sooch, David R. Welland
  • Publication number: 20020150151
    Abstract: An improved digital capacitive isolation barrier system is provided that is suitable for use in a telephone or modem where the locally powered circuits must be effectively isolated from the public telephone system, while permitting data transfer across the barrier. In particular, an automatic ADC offset calibration system is provided for determining the magnitude of the ADC offset signal required in the system during a calibration operation, and for providing the calibrated ADC offset signal during normal operation of the isolation barrier system. A modified hybrid circuit is provided for isolating the system input from the telephone line during calibration, and for completing the calibration loop. Fixed bias signals are also provided for the ADC and for a DAC in the system. In a preferred embodiment, the ADC is located on the isolated side of the isolation barrier, while the integrator and register that determine and hold the offset signal are located on the powered side of the isolation barrier.
    Type: Application
    Filed: June 4, 2002
    Publication date: October 17, 2002
    Applicant: Silicon Laboratories Inc.
    Inventors: Andrew W. Krone, Timothy J. Dupuis, Jeffrey W. Scott, Navdeep S. Sooch, David R. Welland
  • Patent number: 6456712
    Abstract: A communication system of the present invention utilizes ring detection circuitry on both sides of an isolation barrier. More particularly, the ring detection circuitry may include ring burst circuitry on the phone line side of the isolation barrier and ringer timing circuits on the powered side of the isolation barrier. The digital burst peak signal may be transmitted through the isolation barrier to the ringer timing circuits. By splitting the ring detection circuitry so that the ringer timing circuits are placed on the powered side of the isolation barriers, a significant reduction in the power usage on the phone line side of the barrier related to the ring detection function may occur. The outputs of the ringing timing circuits may be provided to circuits on either side of the isolation barrier. Thus, the ring detection function may be accomplished in a system utilizing an efficient bidirectional capacitive barrier while still minimizing power usage on the line side of the barrier.
    Type: Grant
    Filed: March 4, 1998
    Date of Patent: September 24, 2002
    Assignee: Silicon Laboratories Inc.
    Inventors: Jerrell P. Hein, Jeffrey W. Scott, Navdeep S. Sooch, David R. Welland
  • Publication number: 20020130801
    Abstract: An isolation system is provided that is suitable for use in telephony, medical instrumentation, industrial process control and other applications. Preferred embodiments of the invention comprise a capacitive isolation barrier across which a digital signal is communicated. The system provides a means of communication across the isolation barrier that is highly immune to amplitude and phase noise interference. Clock recovery circuitry may be employed on one side of the isolation barrier to extract timing information from the digital signal communicated across the barrier, and to filter the effects of phase noise introduced at the barrier. Delta-sigma converters may be disposed on both sides of the isolation barrier to convert signals between analog and digital domains. An isolated power supply may also be provided on the isolated side of the barrier, whereby direct current is generated in response to the digital data received across the isolation barrier.
    Type: Application
    Filed: August 27, 2001
    Publication date: September 19, 2002
    Applicant: Silicon Laboratories, Inc.
    Inventors: Jeffrey W. Scott, Navdeep S. Sooch, David R. Welland
  • Patent number: 6442271
    Abstract: A method and apparatus are provided for maintaining communication across an isolation barrier even if the external circuitry to which it is connected enters a low-power mode. In normal operation the isolation barrier local clock is synchronized with a clock signal provided by the external circuitry. If the external circuitry enters a low-power mode, its clock signal often slows or stops. In that case, the local clock in the isolation barrier switches to a free-running mode, wherein a VCO voltage input is provided by a bias voltage generator instead of by a PLL circuit. The VCO thus continues to provide a local clock signal in order to allow communication of information across the isolation barrier even if the external circuitry is not active. This enables the isolation barrier to receive and process an external signal, such as a ring signal, in low-power mode.
    Type: Grant
    Filed: March 4, 1998
    Date of Patent: August 27, 2002
    Assignee: Silicon Laboratories, Inc.
    Inventors: George Tyson Tuttle, Jerrell P. Hein, Timothy J. Dupuis, Jeffrey W. Scott, Navdeep S. Sooch, David R. Welland
  • Patent number: 6442213
    Abstract: An improved digital capacitive isolation barrier system is provided that is suitable for use in a telephone or modem where the locally powered circuits must be effectively isolated from the public telephone system, while permitting data transfer across the barrier. In particular, an automatic ADC offset calibration system is provided for determining the magnitude of the ADC offset signal required in the system during a calibration operation, and for providing the calibrated ADC offset signal during normal operation of the isolation barrier system. A modified hybrid circuit is provided for isolating the system input from the telephone line during calibration, and for completing the calibration loop. Fixed bias signals are also provided for the ADC and for a DAC in the system. In a preferred embodiment, the ADC is located on the isolated side of the isolation barrier, while the integrator and register that determine and hold the offset signal are located on the powered side of the isolation barrier.
    Type: Grant
    Filed: March 4, 1998
    Date of Patent: August 27, 2002
    Assignee: Silicon Laboratories Inc.
    Inventors: Andrew W. Krone, Timothy J. Dupuis, Jeffrey W. Scott, Navdeep S. Sooch, David R. Welland
  • Patent number: 6430229
    Abstract: An isolation system is provided that is suitable for use in telephony, medical instrumentation, industrial process control and other applications. Preferred embodiments of the invention comprise a capacitive isolation barrier across which a digital signal is communicated. The system provides a means of communication across the isolation barrier that is highly immune to amplitude and phase noise interference. Clock recovery circuitry may be employed on one side of the isolation barrier to extract timing information from the digital signal communicated across the barrier, and to filter the effects of phase noise introduced at the barrier. Delta-sigma converters may be disposed on both sides of the isolation barrier to convert signals between analog and digital domains. An isolated power supply may also be provided on the isolated side of the barrier, whereby direct current is generated in response to the digital data received across the isolation barrier.
    Type: Grant
    Filed: April 22, 1997
    Date of Patent: August 6, 2002
    Assignee: Silicon Laboratories Inc.
    Inventors: Jeffrey W. Scott, Navdeep S. Sooch, David R. Welland
  • Patent number: 6408034
    Abstract: A communication system having a framing pattern to frame data to be transmitted to a phone line is provided. The data may be framed on one side of an isolation barrier and a clock signal may be extracted from the framed data stream on the other side of the barrier. The data to be framed is provided from an output of a delta-sigma modulator and the framing pattern utilized is a pattern that is unlikely to match the data stream output of the modulator. Thus, an erroneous detection of the framing pattern is unlikely to occur. The framing pattern is chosen to correspond to the expected modulator output for a full scale input signal that is at a frequency higher than the maximum actual frequency of the input data provided to the modulator.
    Type: Grant
    Filed: March 4, 1998
    Date of Patent: June 18, 2002
    Assignee: Silicon Laboratories, Inc.
    Inventors: Andrew W. Krone, Jerrell P. Hein, Jeffrey W. Scott, Navdeep S. Sooch, David R. Welland
  • Patent number: 6389134
    Abstract: A call progress monitor circuit is disclosed for a digital DAA in which digital information is transmitted across an isolation barrier from phone line side circuitry to powered side circuitry. In particular, the call progress monitor circuit of the present invention converts oversampled digital transmit and receive data into analog transmit and receive signals and then combines them to produce a call progress signal that is provided to be fed to a speaker driver circuit. In addition, the call progress signal in one embodiment is filtered with a low pass filter. The call progress monitor circuit in one embodiment includes oversampled digital-to-analog converters, a summing circuit, and a low pass filter. Corresponding methods for monitoring the progress of a call utilizing oversampled digital transmit and receive signals are also disclosed.
    Type: Grant
    Filed: March 4, 1998
    Date of Patent: May 14, 2002
    Assignee: Silicon Laboratories, Inc.
    Inventors: Timothy J. Dupuis, George Tyson Tuttle, Jeffrey W. Scott, Navdeep S. Sooch, David R. Welland
  • Patent number: 6389061
    Abstract: An isolation system is provided that is suitable for use in telephony, medical instrumentation, industrial process control and other applications. Preferred embodiments of the invention comprise a capacitive isolation barrier across which a digital signal is communicated. The system provides a means of communication across the isolation barrier that is highly immune to amplitude and phase noise interference. Clock recovery circuitry may be employed on one side of the isolation barrier to extract timing information from the digital signal communicated across the barrier, and to filter the effects of phase noise introduced at the barrier. Delta-sigma converters may be disposed on both sides of the isolation barrier to convert signals between analog and digital domains. An isolated power supply may also be provided on the isolated side of the barrier, whereby direct current is generated in response to the digital data received across the isolation barrier.
    Type: Grant
    Filed: May 15, 2000
    Date of Patent: May 14, 2002
    Assignee: Silicon Laboratories Inc.
    Inventors: Jeffrey W. Scott, Navdeep S. Sooch, David R. Welland
  • Patent number: 6385235
    Abstract: An isolation system is provided that is suitable for use in telephony, medical instrumentation, industrial process control and other applications. Preferred embodiments of the invention comprise a capacitive isolation barrier across which a digital signal is communicated. The system provides a means of communication across the isolation barrier that is highly immune to amplitude and phase noise interference. Clock recovery circuitry may be employed on one side of the isolation barrier to extract timing information from the digital signal communicated across the barrier, and to filter the effects of phase noise introduced at the barrier. Delta-sigma converters may be disposed on both sides of the isolation barrier to convert signals between analog and digital domains. An isolated power supply may also be provided on the isolated side of the barrier, whereby direct current is generated in response to the digital data received across the isolation barrier.
    Type: Grant
    Filed: March 4, 1998
    Date of Patent: May 7, 2002
    Assignee: Silicon Laboratories, Inc.
    Inventors: Jeffrey W. Scott, Navdeep S. Sooch, David R. Welland
  • Patent number: 6359983
    Abstract: A method and apparatus are provided for reducing the amplitude of signals that often are inadvertently coupled to a telephone line from an isolation barrier system, or that cause undesirable interference within the circuitry of the isolation barrier system. Such signals have undesirable peaks in the frequency domain (spectral peaks) due to the existence of periodicities in the data signal that is transmitted across the isolation barrier. Such spectral peaks are reduced by this invention, which comprises randomizing or scrambling the data signal before it crosses the isolation barrier, and descrambling the data after it has crossed the isolation barrier. In one embodiment, the data signal is scrambled by combining it with a random bit stream (or a pseudo random bit stream), which effectively “whitens” the resulting scrambled signal, thus removing spectral peaks that exist in the original data signal.
    Type: Grant
    Filed: March 4, 1998
    Date of Patent: March 19, 2002
    Assignee: Silicon Laboratories, Inc.
    Inventors: Andrew W. Krone, Jeffrey W. Scott, Navdeep S. Sooch, David R. Welland