Abstract: Systems, methods and apparatus to determine a programming mode of a set of memory cells without having bit values stored in the memory cells to include an identifier of the programming mode. During the test of which of the memory cells in the set is in a lowest voltage region, which is a common operation for reading the memory cells programmed in different mode, the statistics of the memory cells found to be in the lowest voltage region can be compared to the known, different behaviors of the memory cell set programmed in different modes. A match with the behavior of one of the modes can be used to identify the matching mode as the programming mode of the set of memory cells.

Abstract: Methods, systems, and devices for dynamic read voltage techniques are described. In some examples, a memory device may include one or more partitions made up of multiple disjoint subsets of memory arrays. The memory device may receive a read command to read the one or more partitions and enter a drift determination phase. During the drift determination phase, the memory device may concurrently apply a respective voltage of a set of voltages to each disjoint subset and determine a quantity of memory cells in each disjoint subset that have a threshold voltage below the applied voltage. Based on a comparison between the determined quantity of memory cells and a predetermined quantity of memory cells, the memory device may select a voltage from the set of voltages and utilize the selected voltage to read the one or more partitions.

Abstract: Systems, methods and apparatus to implement bipolar read retry. In response to a determination that a first result of reading a set of memory cells using a first magnitude of read voltage is erroneous, a second magnitude of read voltage, greater than the first magnitude, is identified for the bipolar read retry. In the retry, a controller uses voltage drivers to apply, to the set of memory cells, first voltages of the second magnitude in a first polarity to obtain a second result of reading the set of memory cells and, after the second result is generated and in parallel with decoding the second result, apply second voltages of the second magnitude in a second polarity, opposite to the first polarity.

Abstract: Systems, methods, and apparatus related to memory devices. In one approach, a memory device has a memory array including memory cells. A controller of the memory device evaluates background leakage in order to select a write voltage to apply to a memory cell when performing a programming operation. The write voltage is dynamically selected from two or more write voltages. These write voltages include a first write voltage that is a normal or default voltage, and a second write voltage that is a boosted write voltage. The controller applies a pre-sensing voltage and pre-read voltage to the memory cell, and determines first and second respective currents that result from applying these voltages. In response to determining that the first current exceeds a first threshold (indicating background leakage), and the second current is below a second threshold that is greater than the first threshold (indicating that the memory cell does not snap), the controller selects the second (boosted) write voltage.

Abstract: Systems, methods and apparatus to determine a programming mode of a set of memory cells without having bit values stored in the memory cells to include an identifier of the programming mode. During the test of which of the memory cells in the set is in a lowest voltage region, which is a common operation for reading the memory cells programmed in different mode, the statistics of the memory cells found to be in the lowest voltage region can be compared to the known, different behaviors of the memory cell set programmed in different modes. A match with the behavior of one of the modes can be used to identify the matching mode as the programming mode of the set of memory cells.

Abstract: Systems, methods and apparatus to determine a programming mode of a set of memory cells that store an indicator of the programming mode. In response to a command to read the memory cells in a memory device, a first read voltage is applied to the memory cells to identify a first subset of the memory cells that become conductive under the first read voltage. The determination of the first subset is configured as an operation common to different programming modes. Based on whether the first subset of the memory cell includes one or more predefined memory cells, the memory device determines a programming mode of memory cells. Once the programming mode is identified from the common operation, the memory device can further execute the command to determine a data item stored, via the programming mode, in the memory cells.

Abstract: Systems, methods and apparatus to determine, in response to a command to write data into a set of memory cells, a programming mode of a set of memory cell to optimize performance in retrieving the data back from the set of memory cells. For example, based on usages of a memory region containing the memory cell set, a predictive model can be used to identify a combination of an amount of redundant information to be stored into the memory cells in the set and a programming mode of the memory cells to store the redundant information. Increasing the amount of redundant information can increase error recovery capability but increase bit error rate and/or increase time to read. The predictive model is trained to predict the combination to optimize read performance.

Abstract: An example apparatus includes a three-dimensional (3D) memory array including a sense line and a plurality of vertical stacks. Each respective on of the vertical stacks includes a different respective portion of the sense line, a first memory cell coupled to that portion of the sense line, a second memory cell coupled to that portion of the sense line, a first access line coupled to the first memory cell and a second access line coupled to the second memory cell. The first and second access lines are perpendicular to the sense line.

Abstract: Methods, systems, and devices for accessing a multi-level memory cell are described. The memory device may perform a read operation that includes pre-read portion and a read portion to access the multi-level memory cell. During the pre-read portion, the memory device may apply a plurality of voltages to a plurality of memory cells to identify a likely distribution of memory cells storing a first logic state. During the read portion, the memory device may apply a first read voltage to a memory cell based on performing the pre-read portion. The memory device may apply a second read voltage to the memory cell during the read portion that is based on the first read voltage. The memory device may determine the logic state stored by the memory cell based on applying the first read voltage and the second read voltage.

Abstract: Systems, methods, and apparatus related to memory devices. In one approach, a memory device has a memory array including memory cells. A controller of the memory device applies multiple pre-read voltages to memory cells prior to performing write operations on the memory cells. The controller applies a first pre-read voltage to determine which of the memory cells have a sensed current that exceeds a threshold. In response to determining that a percentage of the memory cells exceeding the threshold is too low (e.g., below a fixed limit), the controller determines to apply a second pre-read voltage to the memory cells. The second pre-read voltage has a greater magnitude than the first pre-read voltage, and can be applied to ensure greater reliability in properly determining the existing programming state of the memory cells. The controller then applies write voltages to the memory cells as appropriate based on target logic states for each memory cell and the programming mode to be used by the controller.

Abstract: A memory device having memory cells, voltage drivers, and a controller configured to determine, based on an attribute of a memory cell, whether to apply a drift cancellation pulse that is in the opposite polarity of a programming pulse configured to place the memory cell in a state to represent a bit of data. If the drift in the state of the memory cell from a previous programming operation to write data into the memory cell is predicted to be insufficient to prevent the selection of the memory cell during the application of the programming pulse, the drift cancellation pulse is skipped. Otherwise, the drift cancellation pulse is applied in the opposite polarity of the programming pulse.

Abstract: The present disclosure includes apparatuses, methods, and systems for performing refresh operations on memory cells. A memory can include a group of memory cells and one or more additional memory cells whose data state is indicative of whether to refresh the group of memory cells. Circuitry is configured to apply a first voltage pulse to the group of memory cells to sense a data state of the memory cells of the group, apply, while the first voltage pulse is applied to the group of memory cells, a second voltage pulse having a greater magnitude than the first voltage pulse to the one or more additional memory cells to sense a data state of the one or more additional memory cells, and determine whether to perform a refresh operation on the group of memory cells based on the sensed data state of the one or more additional memory cells.

Abstract: Systems, methods, and apparatus related to memory devices. In one approach, a memory device has a memory array including memory cells. A controller of the memory device evaluates background leakage in order to select a write voltage to apply to a memory cell when performing a programming operation. The write voltage is dynamically selected from two or more write voltages. These write voltages include a first write voltage that is a normal or default voltage, and a second write voltage that is a boosted write voltage. The controller applies a pre-sensing voltage and pre-read voltage to the memory cell, and determines first and second respective currents that result from applying these voltages. In response to determining that the first current exceeds a first threshold (indicating background leakage), and the second current is below a second threshold that is greater than the first threshold (indicating that the memory cell does not snap), the controller selects the second (boosted) write voltage.

Abstract: Systems, methods, and apparatus related to memory devices. In one approach, a memory device has a memory array including memory cells. A controller of the memory device evaluates background leakage in order to select a write voltage to apply to a memory cell when performing a programming operation. The write voltage is dynamically selected from two or more write voltages. These write voltages include a first write voltage that is a normal or default voltage, and a second write voltage that is a boosted write voltage. The controller applies a pre-sensing voltage and pre-read voltage to the memory cell, and determines first and second respective currents that result from applying these voltages. In response to determining that the first current exceeds a first threshold (indicating background leakage), and the second current is below a second threshold that is greater than the first threshold (indicating that the memory cell does not snap), the controller selects the second (boosted) write voltage.

Abstract: The present disclosure includes apparatuses, methods, and systems for multi-state programming of memory cells. An embodiment includes a memory having a plurality of memory cells, and circuitry configured to program a memory cell of the plurality of memory cells to one of four possible data states by applying a first voltage pulse to the memory cell wherein the first voltage pulse has a first polarity and a first magnitude, and applying a second voltage pulse to the memory cell wherein the second voltage pulse has a second polarity and a second magnitude, and the second voltage pulse is applied for a shorter duration than the first voltage pulse.

Abstract: Systems, methods, and apparatus related to memory devices. In one approach, a memory device has a memory array including memory cells. A controller of the memory device applies multiple pre-read voltages to memory cells prior to performing write operations on the memory cells. The controller applies a first pre-read voltage to determine which of the memory cells have a sensed current that exceeds a threshold. In response to determining that a percentage of the memory cells exceeding the threshold is too low (e.g., below a fixed limit), the controller determines to apply a second pre-read voltage to the memory cells. The second pre-read voltage has a greater magnitude than the first pre-read voltage, and can be applied to ensure greater reliability in properly determining the existing programming state of the memory cells. The controller then applies write voltages to the memory cells as appropriate based on target logic states for each memory cell and the programming mode to be used by the controller.

Abstract: An example apparatus includes a three-dimensional (3D) memory array including a sense line and a plurality of vertical stacks. Each respective on of the vertical stacks includes a different respective portion of the sense line, a first memory cell coupled to that portion of the sense line, a second memory cell coupled to that portion of the sense line, a first access line coupled to the first memory cell and a second access line coupled to the second memory cell. The first and second access lines are perpendicular to the sense line.

Abstract: Methods, systems, and devices for accessing a multi-level memory cell are described. The memory device may perform a read operation that includes pre-read portion and a read portion to access the multi-level memory cell. During the pre-read portion, the memory device may apply a plurality of voltages to a plurality of memory cells to identify a likely distribution of memory cells storing a first logic state. During the read portion, the memory device may apply a first read voltage to a memory cell based on performing the pre-read portion. The memory device may apply a second read voltage to the memory cell during the read portion that is based on the first read voltage. The memory device may determine the logic state stored by the memory cell based on applying the first read voltage and the second read voltage.

Abstract: The present disclosure includes apparatuses, methods, and systems for multi-state programming of memory cells. An embodiment includes a memory having a plurality of memory cells, and circuitry configured to program a memory cell of the plurality of memory cells to one of four possible data states by applying a first voltage pulse to the memory cell wherein the first voltage pulse has a first polarity and a first magnitude, and applying a second voltage pulse to the memory cell wherein the second voltage pulse has a second polarity and a second magnitude, and the second voltage pulse is applied for a shorter duration than the first voltage pulse.

Abstract: Methods, systems, and devices for data-based polarity write operations are described. A write command may cause a set of data to be written to a set of memory cells. To write the set of data, a write operation that applies voltages across the memory cells based on a logic state of data to be written to the memory cells may be used. During a first interval of the write operation, a voltage may be applied across a memory cell based on a logic state of a data bit to be written to the memory cell. During a second interval of the write operation, a voltage may be applied across the memory cell based on an amount of charge conducted by the memory cell during the first interval.