Patents by Inventor Nevil N Gajera

Nevil N Gajera has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Multistage set procedure for phase change memory
    Patent number: 9892785
    Abstract: Phase change material can be set with a multistage set process. Set control logic can heat a phase change semiconductor material (PM) to a first temperature for a first period of time. The first temperature is configured to promote nucleation of a crystalline state of the PM. The control logic can increase the temperature to a second temperature for a second period of time. The second temperature is configured to promote crystal growth within the PM. The nucleation and growth of the crystal set the PM to the crystalline state. The multistage ramping up of the temperature can improve the efficiency of the set process relative to traditional approaches.
    Type: Grant
    Filed: February 24, 2017
    Date of Patent: February 13, 2018
    Assignee: Intel Corporation
    Inventors: Sanjay Rangan, Kiran Pangal, Nevil N Gajera, Lu Liu, Gayathri Rao Subbu
  • TECHNIQUES TO MITIGATE BIAS DRIFT FOR A MEMORY DEVICE
    Publication number: 20170287533
    Abstract: Examples may include techniques to mitigate bias drift for memory cells of a memory device. A first memory cell coupled with a first word-line and a bit-line is selected for a write operation. A second memory cell coupled with a second word-line and the bit-line is de-selected for the write operation. First and second bias voltages are applied to the first word-line and the bit-line during the write operation to program the first memory cell. A third bias voltage is applied to the second word-line during the write operation to reduce or mitigate voltage bias to the second memory cell due to the second bias voltage applied to the bit-line to program the first memory cell.
    Type: Application
    Filed: January 25, 2017
    Publication date: October 5, 2017
    Applicant: Intel Corporation
    Inventors: Rakesh Jeyasingh, Nevil N. Gajera, Mase J. Taub, Kiran Pangal
  • MULTISTAGE SET PROCEDURE FOR PHASE CHANGE MEMORY
    Publication number: 20170169886
    Abstract: Phase change material can be set with a multistage set process. Set control logic can heat a phase change semiconductor material (PM) to a first temperature for a first period of time. The first temperature is configured to promote nucleation of a crystalline state of the PM. The control logic can increase the temperature to a second temperature for a second period of time. The second temperature is configured to promote crystal growth within the PM. The nucleation and growth of the crystal set the PM to the crystalline state. The multistage ramping up of the temperature can improve the efficiency of the set process relative to traditional approaches.
    Type: Application
    Filed: February 24, 2017
    Publication date: June 15, 2017
    Inventors: Sanjay RANGAN, Kiran PANGAL, Nevil N. GAJERA, Lu LIU, Gayathri RAO SUBBU
  • Techniques to mitigate bias drift for a memory device
    Patent number: 9589634
    Abstract: Examples may include techniques to mitigate bias drift for memory cells of a memory device. A first memory cell coupled with a first word-line and a bit-line is selected for a write operation. A second memory cell coupled with a second word-line and the bit-line is de-selected for the write operation. First and second bias voltages are applied to the first word-line and the bit-line during the write operation to program the first memory cell. A third bias voltage is applied to the second word-line during the write operation to reduce or mitigate voltage bias to the second memory cell due to the second bias voltage applied to the bit-line to program the first memory cell.
    Type: Grant
    Filed: March 31, 2016
    Date of Patent: March 7, 2017
    Assignee: Intel Corporation
    Inventors: Rakesh Jeyasingh, Nevil N. Gajera, Mase J Taub, Kiran Pangal
  • Multistage set procedure for phase change memory
    Patent number: 9583187
    Abstract: Phase change material can be set with a multistage set process. Set control logic can heat a phase change semiconductor material (PM) to a first temperature for a first period of time. The first temperature is configured to promote nucleation of a crystalline state of the PM. The control logic can increase the temperature to a second temperature for a second period of time. The second temperature is configured to promote crystal growth within the PM. The nucleation and growth of the crystal set the PM to the crystalline state. The multistage ramping up of the temperature can improve the efficiency of the set process relative to traditional approaches.
    Type: Grant
    Filed: March 28, 2015
    Date of Patent: February 28, 2017
    Assignee: Intel Corporation
    Inventors: Sanjay Rangan, Kiran Pangal, Nevil N Gajera, Lu Liu, Gayathri Rao Subbu
  • MULTISTAGE SET PROCEDURE FOR PHASE CHANGE MEMORY
    Publication number: 20160284404
    Abstract: Phase change material can be set with a multistage set process. Set control logic can heat a phase change semiconductor material (PM) to a first temperature for a first period of time. The first temperature is configured to promote nucleation of a crystalline state of the PM. The control logic can increase the temperature to a second temperature for a second period of time. The second temperature is configured to promote crystal growth within the PM. The nucleation and growth of the crystal set the PM to the crystalline state. The multistage ramping up of the temperature can improve the efficiency of the set process relative to traditional approaches.
    Type: Application
    Filed: March 28, 2015
    Publication date: September 29, 2016
    Inventors: Sanjay Rangan, Kiran Pangal, Nevil N Gajera, Lu Liu, Gayathri Rao Subbu