Abstract: The present disclosure provides a comparator including a non-volatile memory device. The comparator is configured to compare an analog input voltage and a reference voltage and produce a digital output indicative of the comparison result. The digital output may represent a resistance state of the non-volatile memory device in response to the application of the reference voltage and the analog input voltage to the comparator. The present disclosure further provides analog-to-digital converters (ADCs) utilizing the comparator. The non-volatile memory device includes, for example, a memristor device, an MRAM (Magnetoresistive random access memory) device, a phase-change memory (PCM) device, a floating gate, a spintronic device, etc.

Abstract: A laser device for providing light to a LiDAR system comprises a plurality of seed lasers configured to provide multiple seed light beams, at least two of the seed light beams having different wavelengths. An amplifier is optically coupled to the plurality of seed lasers to receive the multiple seed light beams. A power pump is configured to provide pump power to the amplifier, where the amplifier amplifies the multiple seed light beams using the pump power to obtain amplified light beams. A second light coupling unit is configured to demultiplex the amplified light beams to obtain a plurality of output light beams, at least two of the output light beams having wavelengths corresponding to the wavelengths of the at least two seed light beams.

Abstract: The present disclosure provides a voltage divider circuit utilizing non-volatile memory devices. The non-volatile memory device may include, for example, a memristor device, an MRAM (Magnetoresistive random access memory) device, a phase-change memory (PCM) device, a floating gate, a spintronic device, etc. The voltage divider circuit may include one or more first non-volatile memory devices that form a resistor ladder. The resistor ladder may produce a plurality of reference voltages when the resistor ladder is connected between two voltages.

Abstract: Surface pressure measurements on rotating models are important for flow phenomenon identification, understanding flow mechanisms and model aerodynamic design. The disclosure discloses a periodic pressure field measurement system based on the superposed lifetime of pressure sensitive paint, including pressure sensitive paint, a pulse light source, a camera, a synchronizer and a computer. A lifetime superposition method is disclosed in the disclosure for measuring periodic pressure fields of pressure sensitive paint.

Abstract: The disclosure discloses a global pressure acquisition system for a rotating model, including a CCD camera, a signal generator, a stroboscopic pulse LED light source, a photoelectric sensor, a preset counter, and a controller. The disclosure further discloses a global pressure acquisition method for a rotating model. The disclosure has the beneficial effects that, by using the non-contact measuring method disclosed by the present disclosure, a measured model and a flow field are not damaged, a submillimeter-level spatial resolution is achieved, it is ensured that the acquired PSP image of the rotating model is clear, and the signal to noise ratio of the image is increased.

Abstract: The disclosure discloses a measuring device for dynamic characteristics of pressure sensitive paint, including a PSP sample wafer, a dynamic pressure sensor, an oscilloscope, a light source, a photomultiplier tube, a bandpass filter, a loudspeaker, a power amplifier, and a signal generator. The disclosure further discloses a measuring method for dynamic characteristics of pressure sensitive paint. The disclosure has the following beneficial effects: by using the measuring device disclosed by the present disclosure, the continuous sinusoidal pressure wave with any frequency can be generated, and has the frequency precision that does not exceed 0.01 Hz, an optical path is not shielded, high stability is achieved, and the amplitude and phase characteristics of the pressure frequency of the PSP can be precisely captured.

Abstract: An electronic device and communication method are disclosed. The electronic device comprises a processing circuit configured to perform a pre-processing operation on a first one-dimensional sequence of modulation symbols, the pre-processing operation including: performing a dimension-increasing conversion to convert the first one-dimensional sequence of modulation symbols into a first multi-dimensional modulation symbol block; transforming the first multi-dimensional modulation symbol block into a second multi-dimensional modulation symbol block with a first transformation, wherein the first transformation couples each symbol in the first multi-dimensional modulation symbol block with each other; and performing a dimension-decreasing conversion to convert the second multi-dimensional modulation symbol block into a second one-dimensional sequence of modulation symbols, wherein the dimension-decreasing conversion is an inverse process of the dimension-increasing conversion.

Abstract: A crossbar circuit including a crossbar array and a periphery circuit is provided. A resistive random-access memory (RRAM) device of the crossbar array includes a bottom electrode fabricated on a first interconnect layer; a top electrode; and a filament-forming layer fabricated between the bottom electrode and the top electrode. A portion of the filament-forming layer and a portion of the top electrode are fabricated in a via in a first etch stop layer. The crossbar circuit further includes a second etch stop layer fabricated on the top electrode and a dielectric layer fabricated on the second etch stop layer. The top electrode is connected to a first metal via of a second interconnect layer fabricated in the second etch stop layer and the dielectric layer. The periphery circuit includes a metal via of the second interconnect layer that is fabricated in the dielectric layer and the first etch stop layer.

Abstract: The present disclosure provides for a semiconductor device with integrated sensing and processing functionalities. The semiconductor device includes a sensing module configured to generate a plurality of analog sensing signals; one or more crossbar arrays configured to process the analog sensing signals to generate analog preprocessed sensing data; an analog-to-digital converter (ADC) configured to convert the analog preprocessed sensing data into digital preprocessed sensing data; and a machine learning processing unit configured to process the digital preprocessed sensing data utilizing one or more machine learning model. The machine learning processing unit, the crossbar arrays, and the ADC are integrated into a processor wafer of the semiconductor device. The sensing module is integrated in a sensor wafer stacked on the processor wafer.

Abstract: The present disclosure provides for a semiconductor device with integrated sensing and processing functionalities. The semiconductor device includes a sensing module configured to generate a plurality of analog sensing signals; and a machine learning (ML) processor. The sensing module and the ML processor are fabricated on a single wafer. The ML processor includes crossbar arrays that processes the analog sensing signals to generate analog preprocessed sensing data; an analog-to-digital converter (ADC) to convert the analog preprocessed sensing data into digital preprocessed sensing data; and a machine learning processing unit to process the digital preprocessed sensing data utilizing one or more machine learning model.

Abstract: An iron-based metal powder for ultra-high-speed laser cladding comprising chemical composition and mass percentage of the metal powder of: C 0.6˜1.0%, Cr 17.0˜20.0%, Ni 5.0˜6.5%, Mn 2.0˜4.0%, Mo 1.0˜1.5%, Ti 4.0˜6.0%, B 1.0˜1.5%, N 0.08˜0.15%, Si?0.5%, P?0.030%, S?0.030%, balance of Fe and unavoidable impurities, wherein the particle size of the metal powder is 15˜65 ?m, the fluidity is 16˜20 s/50 g.

Abstract: A method for controlling lane changing of a vehicle, including: receiving a lane changing instruction (step 101); acquiring a speed parameter of the vehicle (step 102); according to the speed parameter, determining a controlling coefficient of a predetermined controller (step 103); acquiring a position-deviation parameter and a heading-angle parameter of the vehicle; if the position-deviation parameter is greater than or equal to a first threshold, or, if the heading-angle parameter is greater than or equal to a second threshold, according to the controlling coefficient, the position-deviation parameter and the heading-angle parameter, determining a target steering-wheel steering angle of the vehicle; and according to the target steering-wheel steering angle, controlling the vehicle to perform a lane changing operation, till the position-deviation parameter is less than the first threshold, and the heading-angle parameter is less than the second threshold (step 105).

Abstract: The present invention relates to novel pyridazin-3-yl phenol compounds of formula (I): wherein R1, R2, R3, R4 and R5 are defined herein, which inhibit NOD-like receptor protein 3 (NLRP3) inflammasome activity. The invention further relates to the processes for their preparation, pharmaceutical compositions and medicaments containing them, and their use in the treatment of diseases and disorders mediated by NLRP3.

Abstract: A method for fabricating a forming-free resistive random-access memory (RRAM) device is provided. The method includes: fabricating an RRAM cell and annealing the RRAM cell. The RRAM cell includes: a bottom electrode, a switching oxide layer comprising at least one transition metal oxide; a top electrode, and an interface between the switching oxide layer and the top electrode. In some embodiments, the at least one transition metal oxide includes at least one of HfOx or TaOy, wherein x?2.0, and wherein y?2.5. The interface layer comprises a layer of at least one of Al2O3, MgO, Y2O3, or La2O3. The forming-free RRAM device may be switched to multiple resistance levels without a forming process.

Abstract: An apparatus including a CMOS-compatible resistive random-access memory (RRAM) devices is provided. The apparatus includes a transistor; one or more first interconnect layers fabricated on the transistor; an RRAM device fabricated on the one or more first interconnect layers; and one or more second interconnect layers fabricated on the RRAM device. The RRAM device includes: a bottom electrode; a switching oxide layer including a transition metal oxide; a top electrode; and one or more interface layer including a material that is more chemically stable than the transition metal oxide. In some embodiments, one or more diffusion barriers and/or adhesion layers are fabricated between the RRAM device and the first interconnect layers and/or between the RRAM device and the second interconnect layers.

Abstract: The present disclosure relates to resistive random-access memory (RRAM) devices. In some embodiments, an RRAM device includes: a first electrode; a second electrode comprising a first conductive material; and a switching oxide layer positioned between the first electrode and the second electrode. The switching oxide layer includes at least one transition metal oxide. The first electrode includes a metal nitride layer containing a metal nitride and a metal layer fabricated on the metal nitride layer. The metal layer includes a metal that is not reactive to the at least one transition metal oxide. In some embodiments, the metal nitride in the first electrode includes titanium nitride and/or tantalum nitride. The metal layer includes a layer of a noble metal, such as platinum, palladium, iridium, or ruthenium, etc.

Abstract: Code comparators with nonpolar dynamical switches are provided. An example apparatus comprises: a plurality of row wires; a plurality of column wires; one or more cross-point devices, and a nonpolar volatile two-terminal device formed within a plurality of cross-point devices. Each cross-point device in the plurality of cross-point devices is located at a cross-point between a row in the plurality of row wires and a column in the plurality of column wires; the nonpolar volatile two-terminal device is configured to automatically revert from an ON state to an OFF state, in response to a removal of a bias or signal applied on the nonpolar volatile two-terminal device. The nonpolar volatile two-terminal device is configured to automatically revert from an ON state to an OFF state, in response to a removal of a bias or signal applied on the nonpolar volatile two-terminal device.

Abstract: Technologies relating to crossbar array circuits with proton-based two-terminal volatile memristive devices are disclosed. An example apparatus includes a first bottom conductive layer, a capacitor oxide layer formed on the first bottom conductive layer, a second bottom conductive layer formed on the capacitor oxide layer, a second oxide layer formed on the second bottom conductive layer, and a proton reservoir layer formed on the second oxide layer. In some embodiments, the second bottom conductive layer is H-doped. In some embodiments, a conductance of the second oxide layer is modulated by H-dopant.

Abstract: The present disclosure provides a mode switching method for reducing training overheads in a reconfigurable intelligent surface (RIS)-assisted communication system. The system includes one single-antenna base station, one single-antenna user terminal, and an RIS including N reflection elements, the single-antenna user terminal sends data to the single-antenna base station, however, when a direct link of a user-base station is blocked by a blockage, the data can be sent to the single-antenna base station only via the RIS; the RIS determines a proper reflection solution by using a controller, and dynamically adjusts a phase shift thereof to improve an achievable data rate of the system; and necessary information for phase shift adjustment can be obtained at the base station by uplink training, and transmitted to the RIS controller by using a control link.

Abstract: In accordance with some embodiments of the present disclosure, a memory device is provided. The memory may include a ferroelectric layer including a ferroelectric material interstitially doped with at least one interstitial dopant. The ferroelectric material may include a metal oxide. The interstitial dopant may include an element having an atomic radius that is not greater than an atomic radius of a metal element of the metal oxide. In some embodiments, the metal oxide comprises at least one of hafnium or zirconium. The memory device may be non-volatile. The memory device may be a ferroelectric capacitor (FeCAP), a ferroelectric field-effect transistor (FeFET), a ferroelectric tunneling junction (FTJ), and/or another form of ferroelectric random-access memory (Fe-RAM).