Abstract: The present disclosure relates to an electronic device, a method, and a storage medium for a wireless communication system. Various embodiments for setting guard periods for downlink-to-uplink switching are described. An embodiment relates to an electronic device for a base station used in a TDD communication system, and the electronic device comprises a processing circuit. The processing circuit is configured to: set a first guard period for downlink-to-uplink switching for a first terminal device in a first cell; and set a second guard period for downlink-to-uplink switching for a second terminal device in the first cell, wherein the second guard period for downlink-to-uplink switching is different from the first guard period for downlink-to-uplink switching.

Abstract: Technologies relating to analog-to-analog quantizers with an intrinsic Rectified Linear Unit (ReLU) function designed for in-memory computing are disclosed. An apparatus, in some implementations, includes: a DAC; a first crossbar connected to the DAC; a first analog quantizer connected to the first crossbar; a buffer connected to the first analog quantizer; a second crossbar connected to the buffer; and an ADC connected to the second crossbar.

Abstract: Crossbar arrays with reduced disturbance and methods for programming the same are disclosed. In some implementations, an apparatus comprises: a plurality of rows; a plurality of first columns; a plurality of second columns; a plurality of devices. Each of the plurality of devices is connected among one of the plurality of rows, one of the plurality of first columns, and one of the plurality of second columns. The device further comprises a shared end on the plurality of first columns or the plurality of the second columns connecting to the plurality of the devices in the same row or column; the shared end is grounding or holds a stable voltage potential. In some implementations, one of the devices is: a RRAM, a floating date, a phase change device, an SRAM, a memristor, or a device with tunable resistance. In some implementations the stable voltage potential is a constant DC voltage.

Abstract: Technologies relating to CMOS image sensors with integrated Resistive Random-Access Memory (RRAMs) units that provide energy efficient analog storage, ultra-high speed analog storage, and in-memory computing functions are disclosed. An example CMOS image sensor with integrated RRAM crossbar array circuit includes a CMOS image sensor having multiple pixels configured to receive image signals; a column decoder configured to select the pixels in columns to read out; a row decoder configured to select the pixels in rows to read out; an amplifier configured to amplify first signals received from the CMOS image sensor; a multiplexer configured to sequentially or serially read out second signals received from the amplifier; and a first RRAM crossbar array circuit configured to store third signals received from the multiplexer.

Abstract: Technologies relating to implementing two-stage ramp ADCs in crossbar array circuits for high performance matrix multiplication are disclosed. An example two-stage ramp ADC includes: a transimpedance amplifier configured to convert an input signal from current to voltage; a comparator connected to the transimpedance amplifier; a switch bias set connected to the comparator; a switch side capacitor in parallel with the switch bias set; a ramp side capacitor in parallel with the switch bias set; a ramp generator connected to the comparator via the ramp side capacitor, wherein the ramp generator is configured to generate a ramp signal; a counter; and a memory connected to the comparator, wherein the memory is configured to store an output of the comparator.

Abstract: Technologies relating to increasing the surface area of selectors in crossbar array circuits are provided. An example apparatus includes: a substrate; a first line electrode formed on the substrate; an RRAM stack formed on the first line electrode, wherein the RRAM stack; an isolation layer formed beside the RRAM stack, wherein the isolation layer includes an upper surface and a sidewall, and a height from the upper surface to the first line electrode is 100 nanometers to 10 micrometers; a selector stack formed on the RRAM stack, the sidewall, and the upper surface; and a second line electrode formed on the selector stack.

Abstract: Technologies for reducing series resistance are disclosed. An example method may comprise: forming a first layer on a temporary substrate; forming a second layer on the first layer; etching the first layer and the second layer to form a trench; electroplating a top electrode via the trench, wherein the top electrode partially formed on a top surface of the second layer; removing the first layer and the second layer; forming a curable layer on the temporary substrate and the top electrode; removing the temporary substrate from the curable layer and the top electrode; forming a cross-point device on the curable layer and the top electrode; forming a bottom electrode on the cross-point device; and forming a flexible substrate on the bottom electrode.

Abstract: Provided are an electronic device and a method for wireless communication, and a computer-readable storage medium. The electronic device for wireless communication comprises a processing circuit, wherein the processing circuit is configured to: when it is determined that the electronic device is an overload electronic device with the load thereof being greater than a predetermined threshold value, perform load balancing on the basis of a first beam power of a first beam which is scanned for the initial access of a user equipment and is received by a first user equipment from each adjacent electronic device of at least one adjacent electronic device of the overload electronic device, so as to determine whether the overload electronic device needs to be associated with the first user equipment.

Abstract: In accordance with some embodiments of the present disclosure, an apparatus including a crossbar circuit is provided. The crossbar circuit may include a plurality of cross-point devices with programmable conductance, a transimpedance amplifier (TIA), and an analog-to-digital converter (ADC). The TIA is configured to produce an output voltage based on an input current corresponding to a summation of current from a first plurality of the cross-point devices. The ADC is configured to generate a digital output corresponding to a digital representation of the output voltage of the TIA. To generate the digital output, the ADC is to generate, using a comparator, a first plurality of bits (e.g., MSBs) of the digital output by performing a coarse conversion process and a second plurality of bits (e.g., LSBs) of the digital output by performing a fine conversion process on a sample-and-hold voltage produced in the coarse conversion process.

Abstract: Interface engineering technologies relating to low current RRAM-based crossbar array circuits are disclosed. An apparatus, in some implementations, includes: a substrate; a bottom electrode formed on the substrate; a first geometric confining layer formed on the bottom electrode. The first geometric confining layer comprises a first plurality of pin-holes. The apparatus further comprises a base oxide layer formed on the first geometric confining layer and connected to a first top surface of the bottom electrode via the first pin-holes; and a top electrode formed on the base oxide layer. The base oxide layer comprises one of: TaOx, HfOx, TiOx, ZrOx, or a combination thereof; the first geometric confining layer comprises Al2O3, SiO2, Si3N4, Y2O3, Gd2O3, Sm2O3, CeO2, Er2O3, or a combination thereof.

Abstract: In accordance with some embodiments of the present disclosure, an apparatus including a crossbar circuit is provided. The crossbar circuit may include a plurality of cross-point devices with programmable conductance, a transimpedance amplifier (TIA), and an analog-to-digital converter (ADC). The TIA is configured to produce an output voltage based on an input current corresponding to a summation of current from a first plurality of the cross-point devices. The ADC is configured to generate a digital output corresponding to a digital representation of the output voltage of the TIA. To generate the digital output, the ADC is to generate, using a comparator, a first plurality of bits (e.g., MSBs) of the digital output by performing a coarse conversion process and a second plurality of bits (e.g., LSBs) of the digital output by performing a fine conversion process on a sample-and-hold voltage produced in the coarse conversion process.

Abstract: The present disclosure relates to resistive random-access memory (RRAM) devices. In some embodiments, a RRAM device may include a first electrode, a second electrode, and a switching oxide layer positioned between the first electrode and the second electrode, wherein the switching oxide layer comprises at least one transition metal oxide. The second electrode may include a first layer comprising a first metallic material and a second layer comprising a second metallic material. In some embodiments, the first metallic material and the second metallic material may include titanium and tantalum, respectively. In some embodiments, the second electrode may include an alloy of tantalum. The alloy of tantalum may contain one or more of hafnium, molybdenum, niobium, tungsten, and/or zirconium. In some embodiments, the alloy of tantalum contains a plurality of alloys of tantalum.

Abstract: The present disclosure relates to resistive random-access memory (RRAM) devices. In some embodiments, an RRAM device includes: a first electrode including a metal nitride; a second electrode comprising a first conductive material; and a switching oxide layer positioned between the first electrode and the second electrode. The switching oxide layer includes at least one transition metal oxide. In some embodiments, the metal nitride in the first electrode includes titanium nitride and/or tantalum nitride. The first electrode does not include a non-reactive metal, such as platinum (Pt), palladium (Pd), etc.

Abstract: The present disclosure relates to resistive random-access memory (RRAM) devices. In some embodiments, a RRAM device may include a first electrode; a second electrode comprising an alloy containing tantalum; and a switching oxide layer positioned between the first electrode and the second electrode, wherein the switching oxide layer includes at least one transition metal oxide. The alloy containing tantalum may further contain at least one of hafnium, molybdenum, tungsten, niobium, or zirconium. In some embodiments, the alloy containing tantalum may include one or more of a binary alloy containing tantalum, a ternary alloy containing tantalum, a quaternary alloy containing tantalum, a quinary alloy containing tantalum, a senary alloy containing tantalum, and a high order alloy containing tantalum.

Abstract: An electronic device for a backhaul network, wherein the backhaul network comprises a first communication apparatus connected to a core network and a plurality of second communication apparatuses performing wireless communication with the first communication apparatus, includes: processing circuitry configured to perform control to cause the first communication apparatus comprising the electronic device to: operate as a primary donor; select at least one second communication apparatus of the plurality of second communication apparatuses as a secondary donor; transmit a first indicating signal to the selected at least one second communication apparatus, the first indicating signal comprising node type information indicating the secondary donor; transmit a second indicating signal to a second communication apparatus that are not selected, the second indicating signal comprising node type information indicating a member node.

Abstract: Technologies relating to crossbar array circuits with a 2T1R RRAM cell that includes at least one NMOS transistor and one PMOS transistor for low voltage operations are disclosed. An example apparatus includes a word line; a bit line; a first NMOS transistor; a second PMOS transistor; and an RRAM device. The first NMOS transistor and the second PMOS transistor are in parallel as a pair, wherein the pair connects in series with the RRAM device. The apparatus may further include an inverter, via which the second gate terminal of the second PMOS transistor is connected to the first gate terminal.

Abstract: The present disclosure relates to resistive random-access memory (RRAM) devices. A method for fabricating resistive random-access memory (RRAM) device may include fabricating, on a first electrode of the RRAM device, a first interface layer comprising a first discontinuous film of a first material; fabricating, on the first interface layer, a switching oxide layer comprising at least one transition metal oxide; fabricating a second interface layer on the switching oxide layer; and fabricating a defect engineering layer on the second interface layer. The first material is more chemically stable than the at least one transition metal oxide. The defect engineering layer includes a layer of Ti in some embodiments.

Abstract: Aspects of the present disclosure provide a method for calibrating crossbar-based apparatuses. The method includes obtaining output data of a crossbar-based apparatus may include a plurality of cross-point devices with tunable conductance, where the output data of the crossbar-based apparatus represents computing results of at least one operation performed by the crossbar-based apparatus, and where the output data corresponding to a plurality of settings of a plurality of analog components of the crossbar-based apparatus. The method also includes obtaining, by a processing device, one or more calibration parameters based on the output data of the crossbar-based apparatus, where the one or more calibration parameters correspond to one or more errors associated with one or more of the analog components of the crossbar-based apparatus. The method further includes calibrating the crossbar-based apparatus using the one or more calibration parameters.

Abstract: A microfluidic pressure sensor may include a reference chamber, a sensed volume, a microfluidic channel connecting an interior of the reference chamber to an interior of the sensed volume, a volume of liquid contained and movable within the microfluidic channel while occluding the microfluidic channel and a sensor to output signals indicating positioning of the volume of liquid along the microfluidic channel. Positioning of the volume of liquid along microfluidic channel indicates a pressure of the sensed volume.

Abstract: Aspects of the present disclosure provides a crossbar array circuit including: a crossbar array; a digital-to-analog converter (DAC) configured to receive an input signal to be applied to the crossbar array; a large input resistance connected to the DAC and the crossbar array; and an analog-to-digital converter (ADC) configured to generate output signals of the crossbar array circuit. The crossbar array includes a plurality of cross-point devices connecting a plurality of word lines and a plurality of bit lines. In some embodiments, the crossbar array circuit includes a large output resistance connected to the crossbar array.