Abstract: In accordance with some embodiments of the present disclosure, a memory device is provided. The memory may include a ferroelectric layer including a ferroelectric material interstitially doped with at least one interstitial dopant. The ferroelectric material may include a metal oxide. The interstitial dopant may include an element having an atomic radius that is not greater than an atomic radius of a metal element of the metal oxide. In some embodiments, the metal oxide comprises at least one of hafnium or zirconium. The memory device may be non-volatile. The memory device may be a ferroelectric capacitor (FeCAP), a ferroelectric field-effect transistor (FeFET), a ferroelectric tunneling junction (FTJ), and/or another form of ferroelectric random-access memory (Fe-RAM).

Abstract: Graphene printing is disclosed. A disclosed example graphene printing apparatus includes a gas source to cause a graphene precursor gas to flow across a surface of a substrate, and a localized heat source to locally heat portions of the surface to cause graphene to grow at the portions of the surface based on a printing pattern.

Abstract: In accordance with some embodiments of the present disclosure a tunneling-based selector is provided. The selector includes a multilayer barrier structure fabricated between a first electrode and a second electrode. The multilayer barrier structure includes a first layer of a first van der Waals (vdW) material; a second layer of a second vdW material; and a third layer of a third vdW material. The first layer of the first vdW material is fabricated between the second layer of the second vdW material and the third layer of the third vdW material. The electron affinity of the first layer of the first vdW material is lower than the second electron affinity of the second layer of the second vdW material and the electron affinity of the third layer of the vdW material.

Abstract: The present disclosure provides a mode switching method for reducing training overheads in a reconfigurable intelligent surface (RIS)-assisted communication system. The system includes one single-antenna base station, one single-antenna user terminal, and an RIS including N reflection elements, the single-antenna user terminal sends data to the single-antenna base station, however, when a direct link of a user-base station is blocked by a blockage, the data can be sent to the single-antenna base station only via the RIS; the RIS determines a proper reflection solution by using a controller, and dynamically adjusts a phase shift thereof to improve an achievable data rate of the system; and necessary information for phase shift adjustment can be obtained at the base station by uplink training, and transmitted to the RIS controller by using a control link.

Abstract: A crossbar circuit is provided. The crossbar circuit includes one or more bit lines, one or more word lines, one or more cell devices connected between the bit lines and the word lines, one or more analog-to-digital converters (ADCs) connected to the one or more bit lines, one or more digital-to-analog converters (DACs) connected to the one or more word lines, one or more access controls connected to the one or more cell devices and configured to select a cell device in the one or more cell devices and to program the selected cell device, and a slew rate controller connected to the one or more bit lines. The first slew rate controller is configured to receive an input signal or a bias and output a slew-rate controlled signal.

Abstract: An electronic device comprises a processing circuit configured to: acquire multiple pieces of channel information, which are obtained via multiple channel measurements, about an equivalent channel between a first communication device and a second communication device, wherein in each channel measurement, the second communication device obtains a piece of channel information on the basis of a received reference signal sent from the first communication device, and a reflection signal sent by an intelligent reflecting surface between the first communication device and the second communication device using a corresponding group of reflection parameters to reflect the reference signal; and by means of performing joint processing on multiple groups of reflection parameters used in the multiple channel measurements and the multiple pieces of acquired channel information, determine channel estimations of multiple integration sub-channels which are capable of representing the equivalent channel together with the refle

Abstract: Code comparators with nonpolar dynamical switches are provided. An example apparatus comprises: a plurality of row wires; a plurality of column wires; one or more cross-point devices, and a nonpolar volatile two-terminal device formed within a plurality of cross-point devices. Each cross-point device in the plurality of cross-point devices is located at a cross-point between a row in the plurality of row wires and a column in the plurality of column wires; the nonpolar volatile two-terminal device is configured to automatically revert from an ON state to an OFF state, in response to a removal of a bias or signal applied on the nonpolar volatile two-terminal device. The nonpolar volatile two-terminal device is configured to automatically revert from an ON state to an OFF state, in response to a removal of a bias or signal applied on the nonpolar volatile two-terminal device.

Abstract: According to an example, an apparatus may include an agent delivery device to selectively deliver an agent onto a layer of build material particles. The apparatus may also include an energy source to apply energy onto the layer of build material particles to selectively fuse the build material particles in the layer based upon the locations at which the agent was delivered and a chamber formed of a plurality of walls, in which the agent delivery device and the energy source are housed inside the chamber. The apparatus may further include a vapor source to supply vapor into the chamber to wet the build material particles inside the chamber.

Abstract: The present disclosure relates to resistive random-access memory (RRAM) devices. A method for fabricating an RRAM device includes: fabricating a first bottom electrode and a second bottom electrode on a substrate; fabricating a first isolation layer on the substrate, the first bottom electrode, and the second bottom electrode; fabricating a via in the first isolation layer to expose a portion of the first bottom electrode; fabricating a switching oxide layer on the first isolation layer and the exposed portion of the first bottom electrode; and fabricating a filament-forming layer by etching a portion of the switching oxide layer that extends beyond the via. The portion of the switching oxide layer does not contact the exposed portion of the first bottom electrode. A top electrode is fabricated on the filament-forming layer. A top metal interconnect may be fabricated on the top electrode and a second isolation layer.

Abstract: Technologies relating to using a slew rate controller to reduce disturbance in a crossbar array circuit are disclosed. An example crossbar array circuit includes: one or more bit lines; one or more word lines; one or more 1T1R cells connected between the bit lines and the word lines; one or more ADCs connected to the one or more bit lines; one or more DACs connected to the one or more word lines; one or more access controls connected to the one or more 1T1R cells and configured to select a 1T1R cell in the one or more 1T1R cells and to program the selected 1T1R cell; and a slew rate controller connected to the DACs, wherein the slew rate controller is configured to receive an input signal. The slew rate controller may be configured to transform a step function input signal into a slew rate input signal.

Abstract: Aspects of the present disclosure provide a method for calibrating crossbar-based apparatuses. The method includes obtaining output data of a crossbar-based apparatus may include a plurality of cross-point devices with tunable conductance, where the output data of the crossbar-based apparatus represents computing results of at least one operation performed by the crossbar-based apparatus, and where the output data corresponding to a plurality of settings of a plurality of analog components of the crossbar-based apparatus. The method also includes obtaining, by a processing device, one or more calibration parameters based on the output data of the crossbar-based apparatus, where the one or more calibration parameters correspond to one or more errors associated with one or more of the analog components of the crossbar-based apparatus. The method further includes calibrating the crossbar-based apparatus using the one or more calibration parameters.

Abstract: Switching oxide engineering technologies relating to low current RRAM-based crossbar array circuits are disclosed. A method for fabricating a crossbar device may include forming a bottom electrode on a substrate, forming a switching oxide stack on the bottom electrode, and forming a top electrode on the switching oxide stack. Fabricating the switching oxide stack may include fabricating a plurality of base oxide layers and a plurality of discontinuous oxide layers alternately stacked, wherein the base oxide layers comprise one or more base oxides, wherein the one or more base oxides comprise at least one of TaOx, HfOx, TiOx, or ZrOx.

Abstract: Technologies relating to crossbar array circuits with parallel ground lines are disclosed. An example crossbar array circuit may include a plurality of transistors. The crossbar array circuit may include an RRAM device connected in series with a first transistor and a second transistor; a first bit line connected to the RRAM device; and a grounding line connected to a body terminal of the first transistor. The grounding line is parallel to the first bit line. In some embodiments, the first transistor is an NMOS transistor.

Abstract: In accordance with some embodiments of the present disclosure, an apparatus for performing convolution operations is provided. The apparatus includes a first crossbar circuit comprising a first plurality of cross-point devices; a second crossbar circuit comprising a second plurality of cross-point devices; and a word line logic to apply input signals to the first crossbar circuit and the second crossbar circuit. The word line logic is configured to provide input signals representative of input data to be convolved using one or more two-dimensional convolution kernels and one or more depth-wise convolution kernels. The first crossbar circuit is configured to output a first plurality of output signals representative of a convolution of the input data and the two-dimensional convolution kernels. The second crossbar circuit is configured to output a second plurality of output signals representative of a convolution of the input data and the depth-wise convolution kernels.

Abstract: The present application provides methods for programming a circuit device with reduced disturbances. The methods may include: selecting a first target device on a target row of a plurality of rows and a target column of a plurality of columns; selecting the target row; connecting the plurality of rows other than the target row to a voltage potential with the same polarity as a programming signal; grounding the target column; preparing the programming signal on the target rows; sending a pulse signal enable an access transistor on the target column; and sending the programming signal to pass the first target device.

Abstract: Switching oxide engineering technologies relating to low current RRAM-based crossbar array circuits are disclosed. An apparatus, in some implementations, includes: a substrate; a bottom electrode formed on the substrate; a switching oxide stack formed on the bottom electrode. The switching oxide stack includes one or more base oxide layers and one or more discontinuous oxide layers alternately stacked; An apparatus further includes a top electrode formed on the switching oxide stack. The base oxide layer includes TaOx, HfOx, TiOx, ZrOx, or a combination thereof. The discontinuous oxide layer includes Al2O3, SiO2, Si3N4, Y2O3, Gd2O3, Sm2O3, CeO2, Er2O3, or the combination thereof.

Abstract: Technologies for reducing series resistance are disclosed. An example method may include: forming a first layer on a temporary substrate; forming a second layer on the first layer; etching the first layer and the second layer to form a trench; electroplating a top electrode via the trench, wherein the top electrode partially formed on a top surface of the second layer; removing the first layer and the second layer; forming a curable layer on the temporary substrate and the top electrode; removing the temporary substrate from the curable layer and the top electrode; forming a cross-point device on the curable layer and the top electrode; forming a bottom electrode on the cross-point device; and forming a flexible substrate on the bottom electrode.

Abstract: The present disclosure provides an apparatus, including: a substrate; a bottom electrode formed on the substrate; a first base oxide layer formed on the bottom electrode; a first geometric confining layer formed on the first base oxide layer, wherein the first geometric confining layer comprises a first plurality of pin-holes; a second base oxide layer formed on the first geometric confining layer and connected to a first top surface of the first base oxide layer via the first plurality of pin-holes; and a top electrode formed on the second base oxide layer. The first base oxide layer includes TaOx, HfOx, TiOx, ZrOx, or a combination thereof. The first geometric confining layer comprises Al2O3, SiO2, Si3N4, Y2O3, Gd2O3, Sm2O3, CeO2, Er2O3, or a combination thereof.

Abstract: Technologies relating to crossbar array circuits with parallel grounding lines are disclosed. An example crossbar array circuit includes: a word line; a bit line; a first selector line, a grounding line; a first transistor including a first source terminal, a first drain terminal, a first gate terminal, and a first body terminal; and an RRAM device connected in series with the first transistor. The grounding line is connected to the first body terminal and is grounded and the grounding line parallel to the bit line. The first selector line is connected to the first gate terminal. In some implementations, the RRAM device is connected between the first transistor via the first drain terminal and the word line, and the first source terminal is connected to the bit line.

Abstract: The present application provides an apparatus, including: a substrate; a first line electrode formed on the substrate; an interlayer formed on the first line electrode, a selector stack formed on the interlayer and the first line electrode; an RRAM stack formed on the selector stack; and a second line electrode formed on the RRAM stack. The interlayer comprises an upper surface and a sidewall.