Patents by Inventor Nir Jacob Wakrat
Nir Jacob Wakrat has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20130290606Abstract: Systems and methods are disclosed for power management of a system having non-volatile memory (“NVM”). One or more controllers of the system can optimally turn modules on or off and/or intelligently adjust the operating speeds of modules and interfaces of the system based on the type of incoming commands and the current conditions of the system. This can result in optimal system performance and reduced system power consumption.Type: ApplicationFiled: April 30, 2012Publication date: October 31, 2013Applicant: Apple Inc.Inventors: Victor E. Alessi, Nicholas C. Seroff, Arjun Kapoor, Nir Jacob Wakrat, Anthony Fai
-
Patent number: 8572335Abstract: In a copyback or read operation for a non-volatile memory subsystem, data page change indicators are used to manage transfers of data pages between a register in non-volatile memory and a controller that is external to the non-volatile memory.Type: GrantFiled: May 21, 2012Date of Patent: October 29, 2013Assignee: Apple Inc.Inventors: Nir Jacob Wakrat, Mark Alan Helm
-
Publication number: 20130283081Abstract: In a non-volatile memory system, physically separate power rails are provided from a host system to a NVM device for independently power cycling a controller and memory array in the NVM device. The controller of the NVM device can send a power cycle request signal to the host system over a host channel, or updates a status register in the NVM device. The host system receives and decodes the power cycle request signal, or reads the status register, and performs the power cycle request, which can include power cycling the controller or the memory array in the NVM device, or both. The power cycle request can be based on a power state of the non-volatile memory system, which can be managed by the controller or the host system, or both.Type: ApplicationFiled: June 14, 2013Publication date: October 24, 2013Inventors: Nir Jacob Wakrat, Anthony Fai, Matthew Byom
-
Patent number: 8519737Abstract: In one implementation, a memory device includes non-volatile memory and a memory controller communicatively coupled to the non-volatile memory over a first bus. The memory device can also include a host device interface through which the memory controller communicates with a host device over a second bus, wherein the host device interface includes an impedance calibration circuit that is adapted to calibrate a signal transmitted over the second bus by host device interface so that a source impedance associated with the signal matches, within a threshold value, a load impedance associated with the host device over the second bus.Type: GrantFiled: July 1, 2011Date of Patent: August 27, 2013Assignee: Apple Inc.Inventors: Anthony Fai, Nicholas Seroff, Nir Jacob Wakrat
-
Patent number: 8516219Abstract: Memory mapping techniques for non-volatile memory are disclosed where logical sectors are mapped into physical pages using data structures in volatile and non-volatile memory. In some implementations, a first lookup table in non-volatile memory maps logical sectors directly into physical pages. A second lookup table in volatile memory holds the location of the first lookup table in non-volatile memory. An index cache tree in volatile memory holds the physical addresses of the most recently written or accessed logical sectors in a compressed format.Type: GrantFiled: July 24, 2009Date of Patent: August 20, 2013Assignee: Apple Inc.Inventors: Daniel Jeffrey Post, Nir Jacob Wakrat, Vadim Khmelnitsky
-
Patent number: 8495332Abstract: A controller, techniques, systems, and devices for optimizing throughput of read operations in flash memory are disclosed. Various optimizations of throughput for read operations can be performed using a controller. In some implementations, read operations for a multi-die flash memory device or system can be optimized to perform a read request with a highest priority (e.g., an earliest received read request) as soon as the read request is ready. In some implementations, the controller can enable optimized reading from multiple flash memory dies by monitoring a read/busy state for each die and switching between dies when a higher priority read operation is ready to begin.Type: GrantFiled: July 24, 2009Date of Patent: July 23, 2013Assignee: Apple Inc.Inventors: Nir Jacob Wakrat, Vadim Khmelnitsky, Daniel Jeffrey Post
-
Patent number: 8489907Abstract: In a non-volatile memory system, physically separate power rails are provided from a host system to a NVM device for independently power cycling a controller and memory array in the NVM device. The controller of the NVM device can send a power cycle request signal to the host system over a host channel, or updates a status register in the NVM device. The host system receives and decodes the power cycle request signal, or reads the status register, and performs the power cycle request, which can include power cycling the controller or the memory array in the NVM device, or both. The power cycle request can be based on a power state of the non-volatile memory system, which can be managed by the controller or the host system, or both.Type: GrantFiled: September 16, 2009Date of Patent: July 16, 2013Assignee: Apple Inc.Inventors: Nir Jacob Wakrat, Anthony Fai, Matthew Byom
-
Patent number: 8472274Abstract: In one implementation, a method for performing memory operations includes receiving, at a memory device, a request to read data from one or more non-volatile memory cells; and retrieving stored temperature information associated with the non-volatile memory cells, wherein the temperature information is associated with a temperature at approximately at a time when the data was written to the non-volatile memory cells. The method can further include reading, by the memory device, the data from the non-volatile memory cells. The method can also include processing the read data based on, at least, the retrieved temperature information; and providing the processed data.Type: GrantFiled: March 2, 2011Date of Patent: June 25, 2013Assignee: Apple Inc.Inventors: Anthony Fai, Nicholas Seroff, Nir Jacob Wakrat
-
Patent number: 8468293Abstract: Techniques for restoring index pages stored in non-volatile memory are disclosed where the index pages map logical sectors into physical pages. Additional data structures in volatile and non-volatile memory can be used by the techniques for restoring index pages. In some implementations, a lookup table associated with data blocks in non-volatile memory can be used to provide information regarding the mapping of logical sectors into physical pages. In some implementations, a lookup table associated with data blocks and a range of logical sectors and/or index pages can be used.Type: GrantFiled: July 24, 2009Date of Patent: June 18, 2013Assignee: Apple Inc.Inventors: Nir Jacob Wakrat, Vadim Khmelnitsky
-
Publication number: 20130151754Abstract: Systems and methods are disclosed for logical block address (“LBA) bitmap usage for a system having non-volatile memory (“NVM”). A bitmap can be stored in volatile memory of the system, where the bitmap can store the mapping statuses of one or more logical addresses. By using the bitmap, the system can determine the mapping status of a LBA without having to access the NVM. In addition, the system can update the mapping status of a LBA with minimal NVM accesses. By reducing the number of NVM accesses, the system can avoid triggering a garbage collection process, which can improve overall system performance.Type: ApplicationFiled: December 12, 2011Publication date: June 13, 2013Applicant: APPLE INC.Inventors: Daniel J. Post, Nir Jacob Wakrat, Vadim Khmelnitsky
-
Publication number: 20130151830Abstract: Systems and methods are disclosed for mount-time reconciliation of data availability. During system boot-up, a non-volatile memory (“NVM”) driver can be enumerated, and an NVM driver mapping can be obtained. The NVM driver mapping can include the actual availability of LBAs in the NVM. A file system can then be mounted, and a file system allocation state can be generated. The file system allocation state can indicate the file system's view of the availability of LBAs. Subsequently, data availability reconciliation can be performed. That is, the file system allocation state and the NVM driver mapping can be overlaid and compared with one another in order to expose any discrepancies.Type: ApplicationFiled: December 12, 2011Publication date: June 13, 2013Applicant: APPLE INC.Inventors: Daniel J. Post, Nir Jacob Wakrat, Vadim Khmelnitsky
-
Publication number: 20130138868Abstract: Systems and methods are provided for improved communications in a nonvolatile memory (“NVM”) system. The system can toggle between multiple communications channels to provide point-to-point communications between a host device and NVM dies included in the system. The host device can toggle between multiple communications channels that extend to one or more memory controllers of the system, and the memory controllers can toggle between multiple communications channels that extend to the NVM dies. Power islands may be incorporated into the system to electrically isolate system components associated with inactive communications channels.Type: ApplicationFiled: November 30, 2011Publication date: May 30, 2013Applicant: APPLE INC.Inventors: Nicholas C. Seroff, Anthony Fai, Nir Jacob Wakrat
-
Patent number: 8438453Abstract: In a memory system, a host controller is coupled to a non-volatile memory (NVM) package (e.g., NAND device). The host controller sends a read command to the NVM package requesting a low latency read operation. Responsive to the read command, a controller in the NVM package retrieves the data and sends the data to an ECC engine for correcting. Following the read command, the host controller sends a read status request command to the controller in the NVM package. Responsive to the read status request, the controller sends a status report to the host controller indicating that some or all of the data is available for transfer to the host controller. Responsive to the report, the host controller transfers the data. An underrun status can be determined to indicate that uncorrected data had been transferred to the host controller.Type: GrantFiled: August 7, 2009Date of Patent: May 7, 2013Assignee: Apple Inc.Inventors: Daniel Jeffrey Post, Nir Jacob Wakrat, Vadim Khmelnitsky
-
Publication number: 20130111298Abstract: Systems and methods are provided for obtaining and using nonvolatile memory (“NVM”) health information. Health information can include a variety of information associated with the performance and reliability of portions of an NVM device, such as the number of errors detected in a portion of NVM or the amount of time required to read from or program a portion of nonvolatile memory. During operation, address specific health information may be stored passively on a host device and provided as part of a command to a memory controller. The memory controller may extract the health information from the command and use the information to execute access requests. After an access request is completed, the memory controller can update the health information and transmit the information back to the host device.Type: ApplicationFiled: October 31, 2011Publication date: May 2, 2013Applicant: APPLE INC.Inventors: Nicholas Seroff, Anthony Fai, Nir Jacob Wakrat
-
Patent number: 8417893Abstract: Memory mapping techniques for non-volatile memory are disclosed where logical sectors are mapped into physical pages using data structures in volatile and non-volatile memory. In some implementations, a first lookup table in non-volatile memory maps logical sectors directly into physical pages. A second lookup table in volatile memory holds the physical address of the first lookup table in non-volatile memory. In some implementations, a cache in volatile memory holds the physical addresses of the most recently written logical sectors. Also disclosed is a block TOC describing block content which can be used for garbage collection and restore operations.Type: GrantFiled: August 18, 2008Date of Patent: April 9, 2013Assignee: Apple Inc.Inventors: Vadim Khmelnitsky, Nir Jacob Wakrat
-
Publication number: 20130073788Abstract: Systems and methods are disclosed for providing a weave sequence counter (“WSC”) for non-volatile memory (“NVM”) systems. The WSC can identify the sequence in which each page of the NVM is programmed. The “weave” aspect can refer to the fact that multiple blocks can be open for programming at once, thus allowing the pages of these blocks to be programmed in a “woven” manner. Systems and methods are also disclosed for providing a host weave sequence counter (“HWSC”). Each time new data is initially programmed to the NVM, this data can be associated with a particular HWSC. The HWSC associated with the data may not change, even when the data is moved to a new page (e.g., for wear leveling purposes and the like). The WSC and HWSC may aid in, for example, performing rollback, building logical-to-physical mappings, determining static-versus-dynamic page statuses, and performing maintenance operations (e.g., wear leveling).Type: ApplicationFiled: September 16, 2011Publication date: March 21, 2013Applicant: APPLE INC.Inventors: Daniel J. Post, Nir Jacob Wakrat, Vadim Khmelnitsky
-
Publication number: 20130073789Abstract: Systems and methods are disclosed for configuring a non-volatile memory (“NVM”). In some embodiments, each block of the NVM can include a block table-of-contents (“TOC”), which can be encoded (e.g., run-length encoded) and dynamically-sized. Thus, as user data is being programmed to a block, the size of a block TOC can be concurrently recalculated and increased only if necessary. In some embodiments, the NVM interface can use a weave sequence stored in the context information and at least one weave sequence associated with each page of a block to determine whether to replay across the pages of the block after system boot-up.Type: ApplicationFiled: September 16, 2011Publication date: March 21, 2013Applicant: APPLE INC.Inventors: Vadim Khmelnitsky, Daniel J. Post, Nir Jacob Wakrat, Matthew J. Byom, Kenneth Herman, Alexander Sanks
-
Patent number: 8397014Abstract: Memory mapping techniques for non-volatile memory are disclosed where logical sectors are mapped into physical pages using data structures in volatile and non-volatile memory. In some implementations, a first lookup table in non-volatile memory maps logical sectors directly into physical pages. A second lookup table in volatile memory holds the physical address of the first lookup table in non-volatile memory. In some implementations, a cache in volatile memory holds the physical addresses of the most recently written logical sectors. Also disclosed is a block TOC describing block content which can be used for garbage collection and restore operations.Type: GrantFiled: August 18, 2008Date of Patent: March 12, 2013Assignee: Apple Inc.Inventors: Vadim Khmelnitsky, Nir Jacob Wakrat
-
Publication number: 20130036254Abstract: In one implementation, a memory subsystem includes non-volatile memory, a memory controller that is communicatively connected to the non-volatile memory over a first bus, a host interface through which the memory controller communicates with a host controller over a second bus, and a joint test action group (JTAG) interface that provides the host controller with access to state information associated with the memory controller. The memory subsystem can be configured to be coupled to a board-level memory device that includes the host controller.Type: ApplicationFiled: August 5, 2011Publication date: February 7, 2013Applicant: APPLE INC.Inventors: Anthony Fai, Nir Jacob Wakrat, Nicholas Seroff
-
Publication number: 20130036255Abstract: In one implementation, a memory subsystem includes a plurality of non-volatile memory dies, a memory controller that is communicatively connected to each of the non-volatile memory dies over one or more first busses, a host interface through which the memory controller communicates with a host over a second bus, and a joint test action group (JTAG) interface through which the host performs a boundary scan of the memory subsystem including, at least, the non-volatile memory dies and the memory controller. The memory subsystem can be configured to be a subunit of a board-level memory device that includes the host.Type: ApplicationFiled: August 5, 2011Publication date: February 7, 2013Applicant: APPLE INC.Inventors: Anthony Fai, Nir Jacob Wakrat, Nicholas Seroff