Patents by Inventor Nobuaki Yasutake
Nobuaki Yasutake has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8923031Abstract: A semiconductor memory device according to an embodiment includes: a memory cell array including a plurality of first lines, a plurality of second lines, and memory cells disposed at each of intersections of the first lines and the second lines; and a control circuit configured to apply a first voltage to a selected first line, apply a second voltage having a voltage value which is smaller than that of the first voltage to a selected second line, and apply a third voltage and a fourth voltage to a non-selected first line and a non-selected second line, respectively. The control circuit is configured to apply a fifth voltage to one of the non-selected first lines that is adjacent to the selected first line, and apply a sixth voltage to one of the non-selected second lines that is adjacent to the selected second line.Type: GrantFiled: February 27, 2013Date of Patent: December 30, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Kei Sakamoto, Masaki Kondo, Nobuaki Yasutake, Takayuki Okamura
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Publication number: 20140347911Abstract: A nonvolatile semiconductor memory device according to an embodiment comprises a memory cell block that includes a memory cell array, the memory cell array including: a plurality of first lines; a plurality of second lines intersecting the plurality of first lines; and a memory cell that is provided at each of intersections of the plurality of first lines and the plurality of second lines and includes a variable resistance element, the memory cell array further including a protective resistance film that is provided respectively at each of the intersections of the plurality of first lines and the plurality of second lines and that is connected in series with the memory cell and ohmically contacts the memory cell, and the protective resistance film being configured from a material having a resistivity of 1˜100 ?·cm.Type: ApplicationFiled: September 11, 2013Publication date: November 27, 2014Applicant: Kabushiki Kaisha ToshibaInventors: Yoichi Minemura, Takayuki Tsukamoto, Takamasa Okawa, Hiroshi Kanno, Atsushi Yoshida, Satoshi Konagai, Nobuaki Yasutake
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Publication number: 20140312295Abstract: According to one embodiment, a memory device includes: a first interconnect extending in a first direction; a plurality of second interconnects extending in a second direction intersecting with the first direction, and having lower ends positioned on the first interconnect; a plurality of third interconnects extending in a third direction intersecting with the second direction; a memory layer provided between the second interconnects and the third interconnects; and selectors respectively provided between the first interconnect and the lower ends of the plurality of second interconnects.Type: ApplicationFiled: September 10, 2013Publication date: October 23, 2014Applicant: Kabushiki Kaisha ToshibaInventors: Nobuaki YASUTAKE, Takayuki OKAMURA
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Patent number: 8796663Abstract: A memory cell comprises a diode layer, a variable resistance layer, a first electrode layer. The diode layer functions as a rectifier element. The variable resistance layer functions as a variable resistance element. The first electrode layer is provided between the variable resistance layer and the diode layer. The first electrode layer comprises a titanium nitride layer configured by titanium nitride. Where a first ratio is defined as a ratio of titanium atoms to nitrogen atoms in a first region in the titanium nitride layer and a second ratio is defined as a ratio of titanium atoms to nitrogen atoms in a second region which is in the titanium nitride layer and is nearer to the variable resistance layer than is the first region, the second ratio is larger than the first ratio.Type: GrantFiled: September 23, 2013Date of Patent: August 5, 2014Assignee: Kabushiki Kaisha ToshibaInventor: Nobuaki Yasutake
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Patent number: 8791552Abstract: A semiconductor memory device includes a cell array layer including a first wire, a memory cell stacked on the first wire, and a second wire formed on the memory cell. The memory cell includes a variable resistance element and a current control element The current control element includes a first conductivity-type semiconductor into which a first impurity is doped, an i-type semiconductor in contact with the first conductivity-type semiconductor, a second conductivity-type semiconductor into which a second impurity is doped, and an impact ionization acceleration unit being formed between the i-type semiconductor and one of the first conductivity-type semiconductor and the second conductivity-type semiconductor.Type: GrantFiled: March 27, 2012Date of Patent: July 29, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Jun Nishimura, Nobuaki Yasutake, Takayuki Okamura
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Patent number: 8772748Abstract: A semiconductor memory device includes a first conductive line, a second conductive line, a cell unit, a silicon nitride film and a double-sidewall film. The first conductive line extends in a first direction. The second conductive line extends in a second direction crossing the first direction. The cell unit includes a phase-change film and a rectifier element connected in series with each other between the first conductive line and the second conductive line. The silicon nitride film is formed on a side surface of the phase-change film. The double-sidewall film includes a silicon oxide film and the silicon nitride film formed on a side surface of the rectifier element.Type: GrantFiled: February 21, 2013Date of Patent: July 8, 2014Assignee: Kabushiki Kaisha ToshibaInventor: Nobuaki Yasutake
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Publication number: 20140021436Abstract: A memory cell comprises a diode layer, a variable resistance layer, a first electrode layer. The diode layer functions as a rectifier element. The variable resistance layer functions as a variable resistance element. The first electrode layer is provided between the variable resistance layer and the diode layer. The first electrode layer comprises a titanium nitride layer configured by titanium nitride. Where a first ratio is defined as a ratio of titanium atoms to nitrogen atoms in a first region in the titanium nitride layer and a second ratio is defined as a ratio of titanium atoms to nitrogen atoms in a second region which is in the titanium nitride layer and is nearer to the variable resistance layer than is the first region, the second ratio is larger than the first ratio.Type: ApplicationFiled: September 23, 2013Publication date: January 23, 2014Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Nobuaki Yasutake
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Publication number: 20140003128Abstract: A semiconductor memory device according to an embodiment includes: a memory cell array including a plurality of first lines, a plurality of second lines, and memory cells disposed at each of intersections of the first lines and the second lines; and a control circuit configured to apply a first voltage to a selected first line, apply a second voltage having a voltage value which is smaller than that of the first voltage to a selected second line, and apply a third voltage and a fourth voltage to a non-selected first line and a non-selected second line, respectively. The control circuit is configured to apply a fifth voltage to one of the non-selected first lines that is adjacent to the selected first line, and apply a sixth voltage to one of the non-selected second lines that is adjacent to the selected second line.Type: ApplicationFiled: February 27, 2013Publication date: January 2, 2014Applicant: Kabushiki Kaisha ToshibaInventors: Kei SAKAMOTO, Masaki KONDO, Nobuaki YASUTAKE, Takayuki OKAMURA
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Publication number: 20140003127Abstract: A semiconductor memory device according to an embodiment includes a memory cell array including memory cells, the memory cells each configured having a current rectifier element and a variable resistance element connected in series therein. Each of the memory cells has formed on aside surface thereof: a first insulating film provided on aside surface of the current rectifier element and the variable resistance element and having a composition ratio of anon-silicon element to silicon which is a first value; a silicon oxide film provided on a side surface of the first insulating film; and a second insulating film provided on aside surface of the silicon oxide film and having a composition ratio of a non-silicon element to silicon which is a second value. The first value is smaller than the second value.Type: ApplicationFiled: February 27, 2013Publication date: January 2, 2014Applicant: Kabushiki Kaisha ToshibaInventors: Kei Sakamoto, Takayuki Okamura, Nobuaki Yasutake, Jun Nishimura
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Publication number: 20130292627Abstract: According to one embodiment, a resistance change memory includes a first interconnect line extending in a first direction, a second interconnect line extending in a second direction intersecting with the first direction, a cell unit which is provided at the intersection of the first interconnect line and the second interconnect line and which includes a memory element and a non-ohmic element that are connected in series. The non-ohmic element has a first semiconductor layer which includes at least one diffusion buffering region and a conductive layer adjacent to the first semiconductor layer. The diffusion buffering region is different in crystal structure from a semiconductor region except for the diffusion buffering region in the first semiconductor layer.Type: ApplicationFiled: July 5, 2013Publication date: November 7, 2013Inventors: Takeshi SONEHARA, Nobuaki YASUTAKE
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Patent number: 8569733Abstract: A memory cell comprises a diode layer, a variable resistance layer, a first electrode layer. The diode layer functions as a rectifier element. The variable resistance layer functions as a variable resistance element. The first electrode layer is provided between the variable resistance layer and the diode layer. The first electrode layer comprises a titanium nitride layer configured by titanium nitride. Where a first ratio is defined as a ratio of titanium atoms to nitrogen atoms in a first region in the titanium nitride layer and a second ratio is defined as a ratio of titanium atoms to nitrogen atoms in a second region which is in the titanium nitride layer and is nearer to the variable resistance layer than is the first region, the second ratio is larger than the first ratio.Type: GrantFiled: December 8, 2011Date of Patent: October 29, 2013Assignee: Kabushiki Kaisha ToshibaInventor: Nobuaki Yasutake
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Patent number: 8507887Abstract: According to one embodiment, a resistance change memory includes a first interconnect line extending in a first direction, a second interconnect line extending in a second direction intersecting with the first direction, a cell unit which is provided at the intersection of the first interconnect line and the second interconnect line and which includes a memory element and a non-ohmic element that are connected in series. The non-ohmic element has a first semiconductor layer which includes at least one diffusion buffering region and a conductive layer adjacent to the first semiconductor layer. The diffusion buffering region is different in crystal structure from a semiconductor region except for the diffusion buffering region in the first semiconductor layer.Type: GrantFiled: September 22, 2010Date of Patent: August 13, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Takeshi Sonehara, Nobuaki Yasutake
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Patent number: 8502183Abstract: According to one embodiment, a semiconductor memory device includes a first conductive line, a second conductive line, a rectifying element, a switching element, a first side wall film and a second side wall film. The first conductive line extends in a first direction. The second conductive line extends in a second direction crossing the first direction. The rectifying element is connected between the first and second conductive lines. The switching element is connected in series with the rectifying element between the first and second conductive lines. The first side wall film is formed on a side surface of the rectifying element. The second side wall film is formed on a side surface of at least one of the first and second conductive lines. At least one of a film type and a film thickness of the second side wall film is different from that of the first side wall film.Type: GrantFiled: July 15, 2010Date of Patent: August 6, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Jun Nishimura, Nobuaki Yasutake, Takeshi Murata
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Patent number: 8450714Abstract: According to one embodiment, a semiconductor memory device includes a first conductive line, a second conductive line, a cell unit, a silicon nitride film, and an insulating film. The first conductive line extends in a first direction. The second conductive line extends in a second direction crossing the first direction. The cell unit includes a phase-change film and a diode including a p-type semiconductor layer and an n-type semiconductor layer. The cell unit is connected in series between the first conductive line and the second conductive line. The silicon nitride film is formed on a side surface of the phase-change film. The insulating film is formed on a side surface of the diode and has a smaller amount of charge trapping than the silicon nitride film.Type: GrantFiled: September 10, 2010Date of Patent: May 28, 2013Assignee: Kabushiki Kaisha ToshibaInventor: Nobuaki Yasutake
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Patent number: 8405061Abstract: A semiconductor memory device includes a first conductive line, a second conductive line, a cell unit, a silicon nitride film and a double-sidewall film. The first conductive line extends in a first direction. The second conductive line extends in a second direction crossing the first direction. The cell unit includes a phase-change film and a rectifier element connected in series with each other between the first conductive line and the second conductive line. The silicon nitride film is formed on a side surface of the phase-change film. The double-sidewall film includes a silicon oxide film and the silicon nitride film formed on a side surface of the rectifier element.Type: GrantFiled: August 30, 2010Date of Patent: March 26, 2013Assignee: Kabushiki Kaisha ToshibaInventor: Nobuaki Yasutake
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Publication number: 20130062590Abstract: According to one embodiment, a method for manufacturing a nonvolatile storage device. The device includes a plurality of first conductive layers each extending in a first direction, a plurality of second conductive layers each extending in a second direction and spaced from the first layers, and memory cells each provided between the first layers and the second layers and including a rectifying element including a semiconductor layer, and a variable resistance element stacked with the rectifying element. The method includes a film formation step, a heating step and a patterning step. The film formation step is configured to form a rectifying element material film including an amorphous semiconductor film. The heating step is configured to heat the rectifying element material film. The patterning step is configured to form the rectifying element including the semiconductor layer by patterning the rectifying element material film after the heating step.Type: ApplicationFiled: June 22, 2012Publication date: March 14, 2013Applicant: Kabushiki Kaisha ToshibaInventors: Takeshi SONEHARA, Nobuaki Yasutake
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Publication number: 20130062589Abstract: A resistance change memory includes a first conductive line extending in a first direction, a second conductive line extending in a second direction which is crossed to the first direction, a cell unit including a memory element and a rectification connected in series between the first and second conductive lines, and a control circuit which is connected to both of the first and second conductive lines. The control circuit controls a value of voltage which is applied to the memory element to change a resistance of the memory element reversibly between first and second values. The rectification includes a p-type semiconductor layer, an n-type semiconductor layer and an intrinsic semiconductor layer therebetween. The rectification has a first diffusion prevention area in the intrinsic semiconductor layer.Type: ApplicationFiled: November 9, 2012Publication date: March 14, 2013Inventors: Nobuaki Yasutake, Takeshi Sonehara
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Patent number: 8384198Abstract: According to one embodiment, a resistance change memory includes a first interconnect extending in a first direction, a second interconnect extending in a second direction intersecting with the first direction, and a cell unit which is provided between the first interconnect and the second interconnect. The cell unit includes a non-ohmic element and a memory element. The non-ohmic element includes a first silicon layer of an n-conductivity type and a conducting layer in contact with a first face of the first silicon layer. The memory element stores data according to a reversible change of a resistance state. The first silicon layer includes a first element and a second element as donor.Type: GrantFiled: November 30, 2010Date of Patent: February 26, 2013Assignee: Kabushiki Kaisha ToshibaInventor: Nobuaki Yasutake
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Publication number: 20120313065Abstract: A semiconductor memory device includes a cell array layer including a first wire, a memory cell stacked on the first wire, and a second wire formed on the memory cell. The memory cell includes a variable resistance element and a current control element The current control element includes a first conductivity-type semiconductor into which a first impurity is doped, an i-type semiconductor in contact with the first conductivity-type semiconductor, a second conductivity-type semiconductor into which a second impurity is doped, and an impact ionization acceleration unit being formed between the i-type semiconductor and one of the first conductivity-type semiconductor and the second conductivity-type semiconductor.Type: ApplicationFiled: March 27, 2012Publication date: December 13, 2012Applicant: Kabushiki Kaisha ToshibaInventors: Jun NISHIMURA, Nobuaki YASUTAKE, Takayuki OKAMURA
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Publication number: 20120145986Abstract: A memory cell comprises a diode layer, a variable resistance layer, a first electrode layer. The diode layer functions as a rectifier element. The variable resistance layer functions as a variable resistance element. The first electrode layer is provided between the variable resistance layer and the diode layer. The first electrode layer comprises a titanium nitride layer configured by titanium nitride. Where a first ratio is defined as a ratio of titanium atoms to nitrogen atoms in a first region in the titanium nitride layer and a second ratio is defined as a ratio of titanium atoms to nitrogen atoms in a second region which is in the titanium nitride layer and is nearer to the variable resistance layer than is the first region, the second ratio is larger than the first ratio.Type: ApplicationFiled: December 8, 2011Publication date: June 14, 2012Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Nobuaki YASUTAKE