Patents by Inventor Nobuhiro Tsuji
Nobuhiro Tsuji has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20170160946Abstract: A memory device includes a semiconductor memory unit, a controller configured to communicate with a host through a serial interface and read data stored in a page of the semiconductor memory unit in response to a read command received through the serial interface, and an error-correcting code (ECC) circuit configured to carry out error correction with respect to data read from each unit region of the page. The controller is further configured to transmit, through the serial interface to the host, information that indicates whether or not a number of error bits detected by the ECC circuit in the data read from each unit region of the page through the error correction is greater than a predetermined value.Type: ApplicationFiled: February 22, 2017Publication date: June 8, 2017Inventors: Shunsuke KODERA, Toshihiko KITAZUME, Kenichirou KADA, Nobuhiro TSUJI, Shinya TAKEDA, Tetsuya IWATA, Yoshio FURUYAMA, Hirosuke NARAI
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Publication number: 20170160972Abstract: A memory system includes a semiconductor memory device including a plurality of blocks, and a controller configured to register a block designated in a protection command as a protected block in a storage region. When the control circuit receives from a host a command to erase the protected block or write to the protected block, the control circuit does not issue a corresponding erase or write command to the semiconductor memory device and notifies the host of the failure to execute the command.Type: ApplicationFiled: February 22, 2017Publication date: June 8, 2017Inventors: Shunsuke KODERA, Toshihiko KITAZUME, Kenichirou KADA, Nobuhiro TSUJI, Shinya TAKEDA, Tetsuya IWATA, Yoshio FURUYAMA, Hirosuke NARAI
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Publication number: 20170161140Abstract: A memory device includes a semiconductor memory unit, a controller circuit configured to communicate with a host through a serial interface, store write data to be written into a page of the semiconductor memory unit in a data buffer, and an error-correcting code (ECC) circuit configured to generate an error correction code from the write data if the ECC circuit is enabled. The controller circuit writes the error correction code with the write data into the page if the ECC circuit is enabled. A maximum column address of the page which is accessible from the host changes depending on whether or not the ECC circuit is enabled.Type: ApplicationFiled: February 22, 2017Publication date: June 8, 2017Inventors: Shunsuke KODERA, Toshihiko KITAZUME, Kenichirou KADA, Nobuhiro TSUJI, Shinya TAKEDA, Tetsuya IWATA, Yoshio FURUYAMA, Hirosuke NARAI
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Patent number: 9620230Abstract: A memory device includes a semiconductor memory unit, and a controller configured to communicate with a host through a serial interface and access the memory semiconductor unit in response to commands received through the serial interface. The controller, in response to a first read command received through the serial interface to read data in a first page of the semiconductor memory unit, issues a first command to the semiconductor memory unit to read data in the first page and, in addition, a second command to read data in a second page that is consecutive to the first page and not specified in the first read command.Type: GrantFiled: March 4, 2016Date of Patent: April 11, 2017Assignee: Kabushiki Kaisha ToshibaInventors: Shinya Takeda, Toshihiko Kitazume, Kenichirou Kada, Nobuhiro Tsuji, Shunsuke Kodera, Tetsuya Iwata, Yoshio Furuyama, Hirosuke Narai
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Publication number: 20170060484Abstract: A memory system includes a semiconductor memory device including a plurality of blocks, and a controller configured to register a block designated in a protection command as a protected block in a storage region. When the control circuit receives from a host a command to erase the protected block or write to the protected block, the control circuit does not issue a corresponding erase or write command to the semiconductor memory device and notifies the host of the failure to execute the command.Type: ApplicationFiled: February 24, 2016Publication date: March 2, 2017Inventors: Shunsuke KODERA, Toshihiko KITAZUME, Kenichirou KADA, Nobuhiro TSUJI, Shinya TAKEDA, Tetsuya IWATA, Yoshio FURUYAMA, Hirosuke NARAI
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Publication number: 20170062063Abstract: A memory device includes a semiconductor memory unit, and a controller configured to communicate with a host through a serial interface and access the memory semiconductor unit in response to commands received through the serial interface. The controller, in response to a first read command received through the serial interface to read data in a first page of the semiconductor memory unit, issues a first command to the semiconductor memory unit to read data in the first page and, in addition, a second command to read data in a second page that is consecutive to the first page and not specified in the first read command.Type: ApplicationFiled: March 4, 2016Publication date: March 2, 2017Inventors: Shinya TAKEDA, Toshihiko KITAZUME, Kenichirou KADA, Nobuhiro TSUJI, Shunsuke KODERA, Tetsuya IWATA, Yoshio FURUYAMA, Hirosuke NARAI
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Publication number: 20170062076Abstract: A memory system includes a plurality of pins for connection to the outside of the memory system, one of the pins being configured to receive a command signal, a memory cell array including a plurality of first memory blocks and a second memory block in which status data indicating which of the first memory blocks is defective, is stored, and a control circuit configured to determine whether or not a first memory block targeted by the command signal is indicated as being defective in the status data. The control circuit allows an operation to be performed on the targeted first memory block in accordance with the command signal when the targeted first memory block is not indicated as being defective, and blocks the operation to be performed on the targeted first memory block when the targeted first memory block is indicated as being defective.Type: ApplicationFiled: March 4, 2016Publication date: March 2, 2017Inventors: Nobuhiro TSUJI, Kenichirou KADA, Shinya TAKEDA, Toshihiko KITAZUME, Shunsuke KODERA, Tetsuya IWATA, Yoshio FURUYAMA, Hirosuke NARAI
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Publication number: 20170062077Abstract: A memory system includes a semiconductor memory device, a controller configured to access the semiconductor module, a plurality of pins for connection to the outside of the memory system, the pins configured to receive and output serial data, and a test circuit. When one of the pins receives serial test data, the test circuit converts the serial test data into parallel test data, and outputs the parallel test data to the semiconductor memory device for writing therein, and when the test circuit receives parallel test data written in the semiconductor memory device, the test circuit converts the parallel test data to serial test data, and outputs the serial test data through one of the pins for test of the memory system.Type: ApplicationFiled: March 4, 2016Publication date: March 2, 2017Inventors: Kenichirou KADA, Shinya TAKEDA, Toshihiko KITAZUME, Mikio TAKASUGI, Nobuhiro TSUJI, Shunsuke KODERA, Tetsuya IWATA, Yoshio FURUYAMA, Hirosuke NARAI
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Publication number: 20170060682Abstract: A memory device includes a semiconductor memory unit, a controller circuit configured to communicate with a host through a serial interface, store write data to be written into a page of the semiconductor memory unit in a data buffer, and an error-correcting code (ECC) circuit configured to generate an error correction code from the write data if the ECC circuit is enabled. The controller circuit writes the error correction code with the write data into the page if the ECC circuit is enabled. A maximum column address of the page which is accessible from the host changes depending on whether or not the ECC circuit is enabled.Type: ApplicationFiled: March 4, 2016Publication date: March 2, 2017Inventors: Shunsuke KODERA, Toshihiko KITAZUME, Kenichirou KADA, Nobuhiro TSUJI, Shinya TAKEDA, Tetsuya IWATA, Yoshio FURUYAMA, Hirosuke NARAI
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Publication number: 20170060676Abstract: A memory device includes a semiconductor memory unit, a controller configured to communicate with a host through a serial interface and read data stored in a page of the semiconductor memory unit in response to a read command received through the serial interface, and an error-correcting code (ECC) circuit configured to carry out error correction with respect to data read from each unit region of the page. The controller is further configured to transmit, through the serial interface to the host, information that indicates whether or not a number of error bits detected by the ECC circuit in the data read from each unit region of the page through the error correction is greater than a predetermined value.Type: ApplicationFiled: March 4, 2016Publication date: March 2, 2017Inventors: Shunsuke KODERA, Toshihiko KITAZUME, Kenichirou KADA, Nobuhiro TSUJI, Shinya TAKEDA, Tetsuya IWATA, Yoshio FURUYAMA, Hirosuke NARAI
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Publication number: 20170060477Abstract: A memory device includes a semiconductor memory unit and a controller circuit configured to communicate with a host through a serial interface and access the semiconductor memory unit in response to commands received through the serial interface. The controller circuit, in response to a host command to read parameters of the memory device, updates at least one of parameters of the memory device stored in the memory device based on operational settings of the memory device, and transmits the updated parameters through the serial interface to the host.Type: ApplicationFiled: March 4, 2016Publication date: March 2, 2017Inventors: Shunsuke KODERA, Toshihiko KITAZUME, Kenichirou KADA, Nobuhiro TSUJI, Shinya TAKEDA, Tetsuya IWATA, Yoshio FURUYAMA, Hirosuke NARAI
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Publication number: 20170062066Abstract: A memory system includes first through fifth pins connectable to a host device to output to the host device a first signal through the third pin and to receive from the host device a first chip select signal through the first pin, a second chip select signal through the second pin, a second signal through the fourth pin, and a clock signal through the fifth pin, an interface circuit configured to recognize, as a command, the second signal received through the fourth pin immediately after detecting the first or second chip select signal, and first and second memory cell arrays.Type: ApplicationFiled: August 10, 2016Publication date: March 2, 2017Inventors: Hirosuke NARAI, Toshihiko KITAZUME, Kenichirou KADA, Nobuhiro TSUJI, Shunsuke KODERA, Tetsuya IWATA, Yoshio FURUYAMA, Shinya TAKEDA
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Patent number: 9492856Abstract: An element wire, an electric wire including the element wire or the element wires, and a process for producing an element wire are provided, by which ductility of a core wire consisting of the element wires can be improved. The element wire is made of metal, at least one element wire being coated with an electrically insulating coating so as to constitute an electric wire. The crystal grains constituting the entire element wire are fine isometric grains. In the process for producing the element wire, an electrically conductive material is subjected to drawing so as to reduce a diameter of the material and subsequently subjected to successive bending along a longitudinal direction of the material.Type: GrantFiled: February 29, 2008Date of Patent: November 15, 2016Assignee: Yazaki CorporationInventors: Kenichi Hanazaki, Satoru Yoshinaga, Nobuhiro Tsuji
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Patent number: 9034721Abstract: A semiconductor substrate is provided in which an alignment mark is formed that can be used for an alignment even after the formation of an impurity diffused layer by the planarization of an epitaxial film. A trench is formed in an alignment region of an N?-type layer formed on an N+-type substrate. This trench is used to leave voids after the formation of a P?-type epitaxial film on the N?-type layer. Then, the voids formed in the N?-type layer can be used as an alignment mark. Thus, such a semiconductor substrate can be used to provide an alignment in the subsequent step of manufacturing the semiconductor apparatus. Thus, the respective components constituting the semiconductor apparatus can be formed at desired positions accurately.Type: GrantFiled: July 31, 2014Date of Patent: May 19, 2015Assignees: SUMCO CORPORATION, DENSO CORPORATIONInventors: Syouji Nogami, Tomonori Yamaoka, Shoichi Yamauchi, Nobuhiro Tsuji, Toshiyuki Morishita
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Patent number: 8956947Abstract: A semiconductor substrate is provided in which an alignment mark is formed that can be used for an alignment even after the formation of an impurity diffused layer by the planarization of an epitaxial film. A trench is formed in an alignment region of an N?-type layer formed on an N+-type substrate. This trench is used to leave voids after the formation of a P?-type epitaxial film on the N?-type layer. Then, the voids formed in the N?-type layer can be used as an alignment mark. Thus, such a semiconductor substrate can be used to provide an alignment in the subsequent step of manufacturing the semiconductor apparatus. Thus, the respective components constituting the semiconductor apparatus can be formed at desired positions accurately.Type: GrantFiled: July 31, 2014Date of Patent: February 17, 2015Assignees: Sumco Corporation, Denso CorporationInventors: Syouji Nogami, Tomonori Yamaoka, Shoichi Yamauchi, Nobuhiro Tsuji, Toshiyuki Morishita
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Publication number: 20140342535Abstract: A semiconductor substrate preventing a void from being generated in an epitaxial film buried in a trench. An N-type first epitaxial film and first trenches are formed on an N+-type substrate body. A P-type second epitaxial film is buried in the first trenches. An N+-type third epitaxial film having the same composition as the first epitaxial film is formed on the first and second epitaxial films to form second trenches. A fourth epitaxial film is grown on the entire interior of the second trenches. The formation of the first and second trenches and the burying of the second and fourth epitaxial films are performed in a plurality of steps. Thus, the aspect ratio of the first and second trenches when the second and fourth epitaxial films are buried can be reduced. As a result, the second and fourth epitaxial films can be buried in the first and second trenches without causing a void.Type: ApplicationFiled: July 31, 2014Publication date: November 20, 2014Inventors: Syouji NOGAMI, Tomonori YAMAOKA, Shoichi YAMAUCHI, Nobuhiro TSUJI, Toshiyuki MORISHITA
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Publication number: 20140342526Abstract: A semiconductor substrate is provided in which an alignment mark is formed that can be used for an alignment even after the formation of an impurity diffused layer by the planarization of an epitaxial film. A trench is formed in an alignment region of an N?-type layer formed on an N+-type substrate. This trench is used to leave voids after the formation of a P?-type epitaxial film on the N?-type layer. Then, the voids formed in the N?-type layer can be used as an alignment mark. Thus, such a semiconductor substrate can be used to provide an alignment in the subsequent step of manufacturing the semiconductor apparatus. Thus, the respective components constituting the semiconductor apparatus can be formed at desired positions accurately.Type: ApplicationFiled: July 31, 2014Publication date: November 20, 2014Inventors: Syouji NOGAMI, Tomonori YAMAOKA, Shoichi YAMAUCHI, Nobuhiro TSUJI, Toshiyuki MORISHITA
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Publication number: 20140342525Abstract: A semiconductor substrate is provided in which an alignment mark is formed that can be used for an alignment even after the formation of an impurity diffused layer by the planarization of an epitaxial film. A trench is formed in an alignment region of an N?-type layer formed on an N+-type substrate. This trench is used to leave voids after the formation of a P?-type epitaxial film on the N?-type layer. Then, the voids formed in the N?-type layer can be used as an alignment mark. Thus, such a semiconductor substrate can be used to provide an alignment in the subsequent step of manufacturing the semiconductor apparatus. Thus, the respective components constituting the semiconductor apparatus can be formed at desired positions accurately.Type: ApplicationFiled: July 31, 2014Publication date: November 20, 2014Inventors: Syouji NOGAMI, Tomonori YAMAOKA, Shoichi YAMAUCHI, Nobuhiro TSUJI, Toshiyuki MORISHITA
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Patent number: 8835276Abstract: A semiconductor substrate is provided in which an alignment mark is formed that can be used for an alignment even after the formation of an impurity diffused layer by the planarization of an epitaxial film. A trench is formed in an alignment region of an N+-type substrate. This trench is used to leave voids after the formation of an N?-type layer. Then, the voids formed in the N+-type substrate can be used as an alignment mark. Thus, such a semiconductor substrate can be used to provide an alignment in the subsequent step of manufacturing the semiconductor apparatus. Thus, the respective components constituting the semiconductor apparatus can be formed at desired positions accurately.Type: GrantFiled: December 9, 2010Date of Patent: September 16, 2014Assignees: Sumco Corporation, Denso CorporationInventors: Syouji Nogami, Tomonori Yamaoka, Shoichi Yamauchi, Nobuhiro Tsuji, Toshiyuki Morishita
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Publication number: 20110076830Abstract: A semiconductor substrate is provided in which an alignment mark is formed that can be used for an aligment even after the formation of an impurity diffused layer by the planarization of an epitaxial film. A trench is formed in an alignment region of an N+-type substrate. This trench is used to leave voids after the formation of an N?-type layer. Then, the voids formed in the N+-type substrate can be used as an alignment mark. Thus, such a semiconductor substrate can be used to provide an alignment in the subsequent step of manufacturing the semiconductor apparatus. Thus, the respective components constituting the semiconductor apparatus can be formed at desired positions accurately.Type: ApplicationFiled: December 9, 2010Publication date: March 31, 2011Applicants: SUMCO CORPORATION, DENSO CORPORATIONInventors: Syouji NOGAMI, Tomonori YAMAOKA, Shoichi YAMAUCHI, Nobuhiro TSUJI, Toshiyuki MORISHITA