Patents by Inventor Nobuhiro Tsuji

Nobuhiro Tsuji has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20100178526
    Abstract: Carbon steel materials having a carbon content of at least 0.15 mass % are caused to abut against each other in a welding part. The rear face side of the welding part is covered by a stainless-steel backing member, and then a tubular probe of a rotary tool is inserted into the front face side of the welding part to weld the metallic materials together. To perform the welding, the maximum attained temperature of the welding part is controlled so as not to exceed 723° C. or 737° C., or the cooling rate of the welding part is controlled to 75° C./s or lower. In this manner, the formation of a martensite phase in the metallic structure of the welding part can be prevented and hard-carbon steel can be welded together at a high intensity.
    Type: Application
    Filed: July 5, 2007
    Publication date: July 15, 2010
    Applicant: OSAKA UNIVERSITY
    Inventors: Hidetoshi Fujii, Nobuhiro Tsuji
  • Patent number: 7656215
    Abstract: A clock generator circuit provides an output clock without an abnormal waveform pulse which causes faulty operation in other function circuits. A phase synchronizing circuit outputs a second clock synchronized with a first clock. A selector signal generator circuit outputs a switching signal when detecting the abnormal waveform pulse in the second clock. A selector outputs the first clock instead of the second clock as the output clock based on the switching signal. A delay circuit delays the second clock input to the selector so that the selector switches the output clock from the second clock to the first clock before the abnormal waveform pulse is input to the selector.
    Type: Grant
    Filed: March 4, 2008
    Date of Patent: February 2, 2010
    Assignee: NEC Electronics Corporation
    Inventor: Nobuhiro Tsuji
  • Publication number: 20090273102
    Abstract: A semiconductor substrate is provided in which an alignment mark is formed that can be used for an aligment even after the formation of an impurity diffused layer by the planarization of an epitaxial film. A trench 11 is formed in an alignment region of an N+-type substrate 1. This trench 11 is used to leave voids 3 after the formation of an N?-type layer 2. Then, the voids 3 formed in the N+-type substrate 1 can be used as an alignment mark. Thus, such a semiconductor substrate can be used to provide an alignment in the subsequent step of manufacturing the semiconductor apparatus. Thus, the respective components constituting the semiconductor apparatus can be formed at desired positions accurately.
    Type: Application
    Filed: October 5, 2006
    Publication date: November 5, 2009
    Inventors: Syouji Nogami, Tomonori Yamaoka, Shoichi Yamauchi, Nobuhiro Tsuji, Toshiyuki Morishita
  • Publication number: 20080213589
    Abstract: An element wire, an electric wire including the element wire or the element wires, and a process for producing an element wire are provided, by which ductility of a core wire consisting of the element wires can be improved. The element wire is made of metal, at least one element wire being coated with an electrically insulating coating so as to constitute an electric wire. The crystal grains constituting the entire element wire are fine isometric grains. In the process for producing the element wire, an electrically conductive material is subjected to drawing so as to reduce a diameter of the material and subsequently subjected to successive bending along a longitudinal direction of the material.
    Type: Application
    Filed: February 29, 2008
    Publication date: September 4, 2008
    Applicants: Yazaki Corporation, Osaka University
    Inventors: Kenichi Hanazaki, Satoru Yoshinaga, Nobuhiro Tsuji
  • Publication number: 20080211063
    Abstract: A semiconductor wafer includes a semiconductor substrate, a semiconductor layer, and an oxide layer. The semiconductor layer is disposed on a surface of the semiconductor substrate and has a crystal structure similar to a crystal structure of the semiconductor substrate. The semiconductor layer includes an element section and a scribe section. The scribe section is disposed to divide the element section into a plurality of portions and is configurated to be used as a cutting allowance for dicing. Each of the portions includes a column structure in which columns having different conductivity types are arranged alternately. The oxide layer is disposed on a surface of the scribe section to be exposed to an outside of the semiconductor device.
    Type: Application
    Filed: February 28, 2008
    Publication date: September 4, 2008
    Applicant: DENSO CORPORATION
    Inventors: Shinichi Adachi, Nobuhiro Tsuji, Shoichi Yamauchi
  • Publication number: 20070084529
    Abstract: A high strength and high ductility low carbon steel having a tensile strength of 800 MPa or more, an uniform elongation of 5% or more, and an elongation to failure of 20% or more which is produced by a method comprising subjecting an ordinary low carbon steel or an ordinary low carbon steel added with boron in an amount being 0.01% or less and effective for accelerating martensitic transformation to processing and heat treatment to prepare a product having coarser size of austenite crystal grains and then to water-quenching, to provide a steel product having a martensite phase in an amount of 90% or more, and subjecting the steel product to a low strain processing, specifically a cold rolling at a total rolling reduction in thickness of 20% or more and less than 80%, and to a low temperature annealing at 500° C. to 600° C., and a method for producing said high strength and high ductility low carbon steel.
    Type: Application
    Filed: October 11, 2006
    Publication date: April 19, 2007
    Inventors: Yoshihiro Saito, Nobuhiro Tsuji, Rintaro Ueji
  • Patent number: 7063751
    Abstract: A trench is formed in a semiconductor substrate through a mask composed of a silicon oxide film formed on the semiconductor substrate. Then, an edge portion at an opening portion of the mask is etched so that the width of the mask opening width is greater than the width of the trench. After that, the inner surface of the trench is smoothed by thermal treatment around at 1000° C. in non-oxidizing or non-nitriding atmosphere under low pressure. Then, the trench is filled with an epitaxial film. After that, the epitaxial film is polished to complete the substrate.
    Type: Grant
    Filed: April 26, 2002
    Date of Patent: June 20, 2006
    Assignee: Denso Corporation
    Inventors: Yasushi Urakami, Shoichi Yamauchi, Hitoshi Yamaguchi, Nobuhiro Tsuji
  • Patent number: 7026248
    Abstract: In a method for manufacturing a semiconductor device of the present invention, a portion of a first epitaxial layer formed in a trench in a silicon substrate is removed by vapor phase etching using a halogenated compound or hydrogen. In this removing process, the portion of the first epitaxial layer is removed at a predetermined temperature higher than that during epitaxial growth of the first epitaxial layer and at a predetermined pressure higher than that during epitaxial growth of the first epitaxial layer. Therefore, stress that would otherwise be concentrated at a bottom portion of the trench is relaxed because rearrangement of the silicon atoms increases.
    Type: Grant
    Filed: January 21, 2003
    Date of Patent: April 11, 2006
    Assignee: Denso Corporation
    Inventors: Shoichi Yamauchi, Nobuhiro Tsuji
  • Publication number: 20060046146
    Abstract: There is provided a new type of non-expanded graphite powder by peeling off a lamination plane within non-expanded graphite particles, which is useful as a conductive carbon material in a positive electrode mix for an alkaline manganese battery. The alkaline manganese battery has an excellent discharge property when the above non-expanded graphite powder are used as the conductive carbon material.
    Type: Application
    Filed: August 23, 2005
    Publication date: March 2, 2006
    Applicant: Nippon Graphite Industries Co., Ltd.
    Inventors: Nobuhiro Tsuji, Hisanori Sugimoto
  • Publication number: 20050045996
    Abstract: A semiconductor device includes a semiconductor substrate and a semiconductor layer. The semiconductor substrate has a main surface that is an Si{100} surface. The substrate has a trench in the main surface. The semiconductor layer is located on surfaces defining the trench to have common crystallographic planes with the semiconductor substrate. The trench is defined by a bottom surface, two long sidewall surfaces that face each other, and two short sidewall surfaces that face each other. The bottom surface and the long sidewall surfaces are Si{100} surfaces.
    Type: Application
    Filed: September 28, 2004
    Publication date: March 3, 2005
    Inventors: Shoichi Yamauchi, Hitoshi Yamaguchi, Jun Sakakibara, Nobuhiro Tsuji
  • Patent number: 6836001
    Abstract: A semiconductor device includes a semiconductor substrate and a semiconductor layer. The semiconductor substrate has a main surface that is an Si{100} surface. The substrate has a trench in the main surface. The semiconductor layer is located on surfaces defining the trench to have common crystallographic planes with the semiconductor substrate. The trench is defined by a bottom surface, two long sidewall surfaces that face each other, and two short sidewall surfaces that face each other. The bottom surface and the long sidewall surfaces are Si{100} surfaces.
    Type: Grant
    Filed: May 21, 2003
    Date of Patent: December 28, 2004
    Assignee: Denso Corporation
    Inventors: Shoichi Yamauchi, Hitoshi Yamaguchi, Jun Sakakibara, Nobuhiro Tsuji
  • Publication number: 20030219933
    Abstract: A semiconductor device includes a semiconductor substrate and a semiconductor layer. The semiconductor substrate has a main surface that is an Si{100} surface. The substrate has a trench in the main surface. The semiconductor layer is located on surfaces defining the trench to have common crystallographic planes with the semiconductor substrate. The trench is defined by a bottom surface, two long sidewall surfaces that face each other, and two short sidewall surfaces that face each other. The bottom surface and the long sidewall surfaces are Si{100} surfaces.
    Type: Application
    Filed: May 21, 2003
    Publication date: November 27, 2003
    Inventors: Shoichi Yamauchi, Hitoshi Yamaguchi, Jun Sakakibara, Nobuhiro Tsuji
  • Publication number: 20030139012
    Abstract: In a method for manufacturing a semiconductor device of the present invention, a portion of a first epitaxial layer formed in a trench in a silicon substrate is removed by vapor phase etching using a halogenated compound or hydrogen. In this removing process, the portion of the first epitaxial layer is removed at a predetermined temperature higher than that during epitaxial growth of the first epitaxial layer and at a predetermined pressure higher than that during epitaxial growth of the first epitaxial layer. Therefore, stress that would otherwise be concentrated at a bottom portion of the trench is relaxed because rearrangement of the silicon atoms increases.
    Type: Application
    Filed: January 21, 2003
    Publication date: July 24, 2003
    Inventors: Shoichi Yamauchi, Nobuhiro Tsuji
  • Publication number: 20020158301
    Abstract: A trench is formed in a semiconductor substrate through a mask composed of a silicon oxide film formed on the semiconductor substrate. Then, an edge portion at an opening portion of the mask is etched so that the width of the mask opening width is greater than the width of the trench. After that, the inner surface of the trench is smoothed by thermal treatment around at 1000° C. in non-oxidizing or non-nitriding atmosphere under low pressure. Then, the trench is filled with an epitaxial film. After that, the epitaxial film is polished to complete the substrate.
    Type: Application
    Filed: April 26, 2002
    Publication date: October 31, 2002
    Inventors: Yasushi Urakami, Shoichi Yamauchi, Hitoshi Yamaguchi, Nobuhiro Tsuji
  • Patent number: 6406982
    Abstract: A trench is formed in a semiconductor substrate through a mask composed of a silicon oxide film formed on the semiconductor substrate. Then, an edge portion at an opening portion of the mask is etched so that an opening width thereof is wider than that of the trench. After that, an inner surface of the trench is smoothed by thermal treatment around at 1000° C. in non-oxidizing or non-nitriding atmosphere under low pressure. Then, the trench is filled with an epitaxial film. After that, the epitaxial film is polished, whereby a semiconductor substrate for forming a semiconductor device is obtained.
    Type: Grant
    Filed: June 1, 2001
    Date of Patent: June 18, 2002
    Assignee: Denso Corporation
    Inventors: Yasushi Urakami, Shoichi Yamauchi, Toshio Sakakibara, Hitoshi Yamaguchi, Nobuhiro Tsuji
  • Publication number: 20010049182
    Abstract: A trench is formed in a semiconductor substrate through a mask composed of a silicon oxide film formed on the semiconductor substrate. Then, an edge portion at an opening portion of the mask is etched so that an opening width thereof is wider than that of the trench. After that, an inner surface of the trench is smoothed by thermal treatment around at 1000° C. in non-oxidizing or non-nitriding atmosphere under low pressure. Then, the trench is filled with an epitaxial film. After that, the epitaxial film is polished, whereby a semiconductor substrate for forming a semiconductor device is obtained.
    Type: Application
    Filed: June 1, 2001
    Publication date: December 6, 2001
    Inventors: Yasushi Urakami, Shoichi Yamauchi, Toshio Sakakibara, Hitoshi Yamaguchi, Nobuhiro Tsuji