Patents by Inventor Noel Rocklein
Noel Rocklein has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10923658Abstract: Some embodiments include a method of forming a memory cell. A first portion of a switching region is formed over a first electrode. A second portion of the switching region is formed over the first portion using atomic layer deposition. The second portion is a different composition than the first portion. An ion source region is formed over the switching region. A second electrode is formed over the ion source region. Some embodiments include a memory cell having a switching region between a pair of electrodes. The switching region is configured to be reversibly transitioned between a low resistive state and a high resistive state. The switching region includes two or more discrete portions, with one of the portions not having a non-oxygen component in common with any composition directly against it in the high resistive state.Type: GrantFiled: June 13, 2019Date of Patent: February 16, 2021Assignee: Micron Technology, Inc.Inventors: Shuichiro Yasuda, Noel Rocklein, Scott E. Sills, Durai Vishak Nirmal Ramaswamy, Qian Tao
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Publication number: 20190296235Abstract: Some embodiments include a method of forming a memory cell. A first portion of a switching region is formed over a first electrode. A second portion of the switching region is formed over the first portion using atomic layer deposition. The second portion is a different composition than the first portion. An ion source region is formed over the switching region. A second electrode is formed over the ion source region. Some embodiments include a memory cell having a switching region between a pair of electrodes. The switching region is configured to be reversibly transitioned between a low resistive state and a high resistive state. The switching region includes two or more discrete portions, with one of the portions not having a non-oxygen component in common with any composition directly against it in the high resistive state.Type: ApplicationFiled: June 13, 2019Publication date: September 26, 2019Applicant: Micron Technology, Inc.Inventors: Shuichiro Yasuda, Noel Rocklein, Scott E. Sills, Durai Vishal Nirmal Ramaswamy, Qian Tao
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Patent number: 10388871Abstract: Some embodiments include a method of forming a memory cell. A first portion of a switching region is formed over a first electrode. A second portion of the switching region is formed over the first portion using atomic layer deposition. The second portion is a different composition than the first portion. An ion source region is formed over the switching region. A second electrode is formed over the ion source region. Some embodiments include a memory cell having a switching region between a pair of electrodes. The switching region is configured to be reversibly transitioned between a low resistive state and a high resistive state. The switching region includes two or more discrete portions, with one of the portions not having a non-oxygen component in common with any composition directly against it in the high resistive state.Type: GrantFiled: October 25, 2016Date of Patent: August 20, 2019Assignee: Micron Technology, Inc.Inventors: Shuichiro Yasuda, Noel Rocklein, Scott E. Sills, Durai Vishak Nirmal Ramaswamy, Qian Tao
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Patent number: 9627501Abstract: Graded dielectric layers and methods of fabricating such dielectric layers provide dielectrics in a variety of electronic structures for use in a wide range of electronic devices and systems. In an embodiment, a dielectric layer is graded with respect to a doping profile across the dielectric layer. In an embodiment, a dielectric layer is graded with respect to a crystalline structure profile across the dielectric layer. In an embodiment, a dielectric layer is formed by atomic layer deposition incorporating sequencing techniques to generate a doped dielectric material.Type: GrantFiled: January 28, 2015Date of Patent: April 18, 2017Assignee: Micron Technology, Inc.Inventors: F. Daniel Gealy, Vishwanath Bhat, Cancheepuram V. Srividya, M. Noel Rocklein
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Publication number: 20170040534Abstract: Some embodiments include a method of forming a memory cell. A first portion of a switching region is formed over a first electrode. A second portion of the switching region is formed over the first portion using atomic layer deposition. The second portion is a different composition than the first portion. An ion source region is formed over the switching region. A second electrode is formed over the ion source region. Some embodiments include a memory cell having a switching region between a pair of electrodes. The switching region is configured to be reversibly transitioned between a low resistive state and a high resistive state. The switching region includes two or more discrete portions, with one of the portions not having a non-oxygen component in common with any composition directly against it in the high resistive state.Type: ApplicationFiled: October 25, 2016Publication date: February 9, 2017Applicant: Micron Technology, Inc.Inventors: Shuichiro Yasuda, Noel Rocklein, Scott E. Sills, Durai Vishak Nirmal Ramaswamy, Qian Tao
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Patent number: 9508931Abstract: Some embodiments include a method of forming a memory cell. A first portion of a switching region is formed over a first electrode. A second portion of the switching region is formed over the first portion using atomic layer deposition. The second portion is a different composition than the first portion. An ion source region is formed over the switching region. A second electrode is formed over the ion source region. Some embodiments include a memory cell having a switching region between a pair of electrodes. The switching region is configured to be reversibly transitioned between a low resistive state and a high resistive state. The switching region includes two or more discrete portions, with one of the portions not having a non-oxygen component in common with any composition directly against it in the high resistive state.Type: GrantFiled: December 29, 2014Date of Patent: November 29, 2016Assignee: Micron Technology, Inc.Inventors: Shuichiro Yasuda, Noel Rocklein, Scott E. Sills, Durai Vishal Nirmal Ramaswamy, Qian Tao
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Patent number: 9397143Abstract: Embodiments of the present disclosure describe a liner for a phase change memory (PCM) array and associated techniques and configurations. In an embodiment, a substrate, an array of phase change memory (PCM) elements disposed on the substrate, wherein individual PCM elements of the array of PCM elements comprise a chalcogenide material and a liner disposed on sidewall surfaces of the individual PCM elements, wherein the liner comprises aluminum (Al), silicon (Si) and oxygen (O). Other embodiments may be described and/or claimed.Type: GrantFiled: December 20, 2013Date of Patent: July 19, 2016Assignee: Intel CorporationInventors: Noel Rocklein, Qian Tao, Zhe Song, Vishwanath Bhat
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Publication number: 20150179706Abstract: Embodiments of the present disclosure describe a liner for a phase change memory (PCM) array and associated techniques and configurations. In an embodiment, a substrate, an array of phase change memory (PCM) elements disposed on the substrate, wherein individual PCM elements of the array of PCM elements comprise a chalcogenide material and a liner disposed on sidewall surfaces of the individual PCM elements, wherein the liner comprises aluminum (Al), silicon (Si) and oxygen (O). Other embodiments may be described and/or claimed.Type: ApplicationFiled: December 20, 2013Publication date: June 25, 2015Inventors: Noel Rocklein, Qian Tao, Zhe Song, Vishwanath Bhat
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Publication number: 20150140776Abstract: Some embodiments include a method of forming a memory cell. A first portion of a switching region is formed over a first electrode. A second portion of the switching region is formed over the first portion using atomic layer deposition. The second portion is a different composition than the first portion. An ion source region is formed over the switching region. A second electrode is formed over the ion source region. Some embodiments include a memory cell having a switching region between a pair of electrodes. The switching region is configured to be reversibly transitioned between a low resistive state and a high resistive state. The switching region includes two or more discrete portions, with one of the portions not having a non-oxygen component in common with any composition directly against it in the high resistive state.Type: ApplicationFiled: December 29, 2014Publication date: May 21, 2015Inventors: Shuichiro Yasuda, Noel Rocklein, Scott E. Sills, Durai Vishal Nirmal Ramaswamy, Qian Tao
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Publication number: 20150137254Abstract: Graded dielectric layers and methods of fabricating such dielectric layers provide dielectrics in a variety of electronic structures for use in a wide range of electronic devices and systems. In an embodiment, a dielectric layer is graded with respect to a doping profile across the dielectric layer. In an embodiment, a dielectric layer is graded with respect to a crystalline structure profile across the dielectric layer. In an embodiment, a dielectric layer is formed by atomic layer deposition incorporating sequencing techniques to generate a doped dielectric material.Type: ApplicationFiled: January 28, 2015Publication date: May 21, 2015Inventors: F. Daniel Gealy, Vishwanath Bhat, Cancheepuram V. Srividya, M. Noel Rocklein
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Patent number: 8993044Abstract: Capacitors and methods of forming capacitors are disclosed, and which include an inner conductive metal capacitor electrode and an outer conductive metal capacitor electrode. A capacitor dielectric region is received between the inner and the outer conductive metal capacitor electrodes and has a thickness no greater than 150 Angstroms. Various combinations of materials of thicknesses and relationships relative one another are disclosed which enables and results in the dielectric region having a dielectric constant k of at least 35 yet leakage current no greater than 1×10?7 amps/cm2 at from ?1.1V to +1.1V.Type: GrantFiled: July 16, 2012Date of Patent: March 31, 2015Assignee: Micron Technology, Inc.Inventors: Rishikesh Krishnan, John Smythe, Vishwanath Bhat, Noel Rocklein, Bhaskar Srinivasan, Jeff Hull, Chris Carlson
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Patent number: 8987863Abstract: Electrical components for microelectronic devices and methods for forming electrical components. One particular embodiment of such a method comprises depositing an underlying layer onto a workpiece, and forming a conductive layer on the underlying layer. The method can continue by disposing a dielectric layer on the conductive layer. The underlying layer is a material that causes the dielectric layer to have a higher dielectric constant than without the underlying layer being present under the conductive layer. For example, the underlying layer can impart a structure or another property to the film stack that causes an otherwise amorphous dielectric layer to crystallize without having to undergo a separate high temperature annealing process after disposing the dielectric layer onto the conductive layer. Several examples of this method are expected to be very useful for forming dielectric layers with high dielectric constants because they avoid using a separate high temperature annealing process.Type: GrantFiled: May 28, 2013Date of Patent: March 24, 2015Assignee: Micron Technology, Inc.Inventors: Rishikesh Krishnan, F. Daniel Gealy, Vidya Srividya, Noel Rocklein
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Publication number: 20150056798Abstract: Some embodiments include methods of forming memory cells. Metal oxide may be deposited over a first electrode, with the deposited metal oxide having a relatively low degree of crystallinity. The degree of crystallinity within the metal oxide may be increased after the deposition of the metal oxide. A dielectric material may be formed over the metal oxide, and a second electrode may be formed over the dielectric material. The degree of crystallinity may be increased with a thermal treatment. The thermal treatment may be conducted before, during, and/or after formation of the dielectric material.Type: ApplicationFiled: October 3, 2014Publication date: February 26, 2015Inventors: Noel Rocklein, Durai Ramaswamy, Dale W. Collins, Swapnil Lengade, Srividya Krishnamurthy, Mark S. Korber
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Patent number: 8951903Abstract: Graded dielectric layers and methods of fabricating such dielectric layers provide dielectrics in a variety of electronic structures for use in a wide range of electronic devices and systems. In an embodiment, a dielectric layer is graded with respect to a doping profile across the dielectric layer. In an embodiment, a dielectric layer is graded with respect to a crystalline structure profile across the dielectric layer. In an embodiment, a dielectric layer is formed by atomic layer deposition incorporating sequencing techniques to generate a doped dielectric material.Type: GrantFiled: February 3, 2012Date of Patent: February 10, 2015Assignee: Micron Technology, Inc.Inventors: Dan Gealy, Vishwanath Bhat, Cancheepuram V. Srividya, M. Noel Rocklein
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Publication number: 20150001674Abstract: Capacitors and methods of forming capacitors are disclosed, and which include an inner conductive metal capacitor electrode and an outer conductive metal capacitor electrode. A capacitor dielectric region is received between the inner and the outer conductive metal capacitor electrodes and has a thickness no greater than 150 Angstroms. Various combinations of materials of thicknesses and relationships relative one another are disclosed which enables and results in the dielectric region having a dielectric constant k of at least 35 yet leakage current no greater than 1×10?7 amps/cm2 at from ?1.1V to +1.1V.Type: ApplicationFiled: September 15, 2014Publication date: January 1, 2015Inventors: Rishikesh Krishnan, John Smythe, Vishwanath Bhat, Noel Rocklein, Bhaskar Srinivasan, Jeff Hull, Chris Carlson
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Patent number: 8921821Abstract: Some embodiments include a method of forming a memory cell. A first portion of a switching region is formed over a first electrode. A second portion of the switching region is formed over the first portion using atomic layer deposition. The second portion is a different composition than the first portion. An ion source region is formed over the switching region. A second electrode is formed over the ion source region. Some embodiments include a memory cell having a switching region between a pair of electrodes. The switching region is configured to be reversibly transitioned between a low resistive state and a high resistive state. The switching region includes two or more discrete portions, with one of the portions not having a non-oxygen component in common with any composition directly against it in the high resistive state.Type: GrantFiled: January 10, 2013Date of Patent: December 30, 2014Assignee: Micron Technology, Inc.Inventors: Shuichiro Yasuda, Noel Rocklein, Scott E. Sills, D. V. Nirmal Ramaswamy, Qian Tao
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Patent number: 8861179Abstract: Capacitors and methods of forming capacitors are disclosed, and which include an inner conductive metal capacitor electrode and an outer conductive metal capacitor electrode. A capacitor dielectric region is received between the inner and the outer conductive metal capacitor electrodes and has a thickness no greater than 150 Angstroms. Various combinations of materials of thicknesses and relationships relative one another are disclosed which enables and results in the dielectric region having a dielectric constant k of at least 35 yet leakage current no greater than 1×10?7 amps/cm2 at from ?1.1V to +1.1V.Type: GrantFiled: August 29, 2012Date of Patent: October 14, 2014Assignee: Micron Technology, Inc.Inventors: Rishikesh Krishnan, John Smythe, Vishwanath Bhat, Noel Rocklein, Bhaskar Srinivasan, Jeff Hull, Chris Carlson
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Patent number: 8859329Abstract: Some embodiments include memory cells having programmable material between a pair of electrodes. The programmable material includes a material selected from the group consisting of a metal silicate with a ratio of metal to silicon within a range of from about 2 to about 6, and metal aluminate with a ratio of metal to aluminum within a range of from about 2 to about 6. Some embodiments include methods of forming memory cells. First electrode material is formed. Programmable material is formed over the first electrode material, with the programmable material including metal silicate and/or metal aluminate. Second electrode material is formed over the programmable material, and then an anneal is conducted at a temperature within a range of from about 300° C. to about 500° C. for a time of from about 1 minute to about 1 hour.Type: GrantFiled: April 23, 2014Date of Patent: October 14, 2014Assignee: Micron Technology, Inc.Inventors: D. V. Nirmal Ramaswamy, Murali Balakrishnan, Alessandro Torsi, Noel Rocklein
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Patent number: 8859382Abstract: Some embodiments include methods of forming memory cells. Metal oxide may be deposited over a first electrode, with the deposited metal oxide having a relatively low degree of crystallinity. The degree of crystallinity within the metal oxide may be increased after the deposition of the metal oxide. A dielectric material may be formed over the metal oxide, and a second electrode may be formed over the dielectric material. The degree of crystallinity may be increased with a thermal treatment. The thermal treatment may be conducted before, during, and/or after formation of the dielectric material.Type: GrantFiled: October 26, 2011Date of Patent: October 14, 2014Assignee: Micron Technology, Inc.Inventors: Noel Rocklein, D. V. Nirmal Ramaswamy, Dale W. Collins, Swapnil Lengade, Srividya Krishnamurthy, Mark Korber
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Publication number: 20140231743Abstract: Some embodiments include memory cells having programmable material between a pair of electrodes. The programmable material includes a material selected from the group consisting of a metal silicate with a ratio of metal to silicon within a range of from about 2 to about 6, and metal aluminate with a ratio of metal to aluminum within a range of from about 2 to about 6. Some embodiments include methods of forming memory cells. First electrode material is formed. Programmable material is formed over the first electrode material, with the programmable material including metal silicate and/or metal aluminate. Second electrode material is formed over the programmable material, and then an anneal is conducted at a temperature within a range of from about 300° C. to about 500° C. for a time of from about 1 minute to about 1 hour.Type: ApplicationFiled: April 23, 2014Publication date: August 21, 2014Applicant: Micron Technology, Inc.Inventors: D. V. Nirmal Ramaswamy, Murali Balakrishnan, Alessandro Torsi, Noel Rocklein