Patents by Inventor Noel Rocklein
Noel Rocklein has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20140191182Abstract: Some embodiments include a method of forming a memory cell. A first portion of a switching region is formed over a first electrode. A second portion of the switching region is formed over the first portion using atomic layer deposition. The second portion is a different composition than the first portion. An ion source region is formed over the switching region. A second electrode is formed over the ion source region. Some embodiments include a memory cell having a switching region between a pair of electrodes. The switching region is configured to be reversibly transitioned between a low resistive state and a high resistive state. The switching region includes two or more discrete portions, with one of the portions not having a non-oxygen component in common with any composition directly against it in the high resistive state.Type: ApplicationFiled: January 10, 2013Publication date: July 10, 2014Applicant: Micron Technology, Inc.Inventors: Shuichiro Yasuda, Noel Rocklein, Scott E. Sills, D.V. Nirmal Ramaswamy, Qian Tao
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Patent number: 8760845Abstract: A capacitor structure includes a storage node; a capacitor dielectric on the storage node; and a plate electrode on the capacitor dielectric. The capacitor dielectric may include a Si-doped ZrO2 layer or crystalline ZrSiOx with a Si/(Zr+Si) content ranging between 4-9% by atomic ratio. The capacitor structure further includes an interfacial TiO2/TiON layer between the storage node and the capacitor dielectric.Type: GrantFiled: February 10, 2012Date of Patent: June 24, 2014Assignee: Nanya Technology Corp.Inventors: Noel Rocklein, Vishwanath Bhat, Chris Carlson
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Patent number: 8753919Abstract: Some embodiments include memory cells having programmable material between a pair of electrodes. The programmable material includes a material selected from the group consisting of a metal silicate with a ratio of metal to silicon within a range of from about 2 to about 6, and metal aluminate with a ratio of metal to aluminum within a range of from about 2 to about 6. Some embodiments include methods of forming memory cells. First electrode material is formed. Programmable material is formed over the first electrode material, with the programmable material including metal silicate and/or metal aluminate. Second electrode material is formed over the programmable material, and then an anneal is conducted at a temperature within a range of from about 300° C. to about 500° C. for a time of from about 1 minute to about 1 hour.Type: GrantFiled: December 12, 2013Date of Patent: June 17, 2014Assignee: Micron Technology, Inc.Inventors: D. V. Nirmal Ramaswamy, Murali Balakrishnan, Alessandro Torsi, Noel Rocklein
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Publication number: 20140106533Abstract: Some embodiments include memory cells having programmable material between a pair of electrodes. The programmable material includes a material selected from the group consisting of a metal silicate with a ratio of metal to silicon within a range of from about 2 to about 6, and metal aluminate with a ratio of metal to aluminum within a range of from about 2 to about 6. Some embodiments include methods of forming memory cells. First electrode material is formed. Programmable material is formed over the first electrode material, with the programmable material including metal silicate and/or metal aluminate. Second electrode material is formed over the programmable material, and then an anneal is conducted at a temperature within a range of from about 300° C. to about 500° C. for a time of from about 1 minute to about 1 hour.Type: ApplicationFiled: December 12, 2013Publication date: April 17, 2014Applicant: Micron Technology, Inc.Inventors: D.V. Nirmal Ramaswamy, Murali Balakrishnan, Alessandro Torsi, Noel Rocklein
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Patent number: 8629421Abstract: Some embodiments include memory cells having programmable material between a pair of electrodes. The programmable material includes a material selected from the group consisting of a metal silicate with a ratio of metal to silicon within a range of from about 2 to about 6, and metal aluminate with a ratio of metal to aluminum within a range of from about 2 to about 6. Some embodiments include methods of forming memory cells. First electrode material is formed. Programmable material is formed over the first electrode material, with the programmable material including metal silicate and/or metal aluminate. Second electrode material is formed over the programmable material, and then an anneal is conducted at a temperature within a range of from about 300° C. to about 500° C. for a time of from about 1 minute to about 1 hour.Type: GrantFiled: October 15, 2012Date of Patent: January 14, 2014Assignee: Micron Technology, Inc.Inventors: D.V. Nirmal Ramaswamy, Murali Balakrishnan, Alessandro Torsi, Noel Rocklein
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Patent number: 8603877Abstract: Some embodiments include dielectric structures. The structures include first and second portions that are directly against one another. The first portion may contain a homogeneous mixture of a first phase and a second phase. The first phase may have a dielectric constant of greater than or equal to 25, and the second phase may have a dielectric constant of less than or equal to 20. The second portion may be entirely a single composition having a dielectric constant of greater than or equal to 25. Some embodiments include electrical components, such as capacitors and transistors, containing dielectric structures of the type described above. Some embodiments include methods of forming dielectric structures, and some embodiments include methods of forming electrical components.Type: GrantFiled: May 1, 2012Date of Patent: December 10, 2013Assignee: Micron Technology, Inc.Inventors: Noel Rocklein, Chris Carlson, Dave Peterson, Cunyu Yang, Praveen Vaidyanathan, Vishwanath Bhat
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Publication number: 20130258550Abstract: Electrical components for microelectronic devices and methods for forming electrical components. One particular embodiment of such a method comprises depositing an underlying layer onto a workpiece, and forming a conductive layer on the underlying layer. The method can continue by disposing a dielectric layer on the conductive layer. The underlying layer is a material that causes the dielectric layer to have a higher dielectric constant than without the underlying layer being present under the conductive layer. For example, the underlying layer can impart a structure or another property to the film stack that causes an otherwise amorphous dielectric layer to crystallize without having to undergo a separate high temperature annealing process after disposing the dielectric layer onto the conductive layer. Several examples of this method are expected to be very useful for forming dielectric layers with high dielectric constants because they avoid using a separate high temperature annealing process.Type: ApplicationFiled: May 28, 2013Publication date: October 3, 2013Inventors: Rishikesh Krishnan, F. Daniel Gealy, Vidya Srividya, Noel Rocklein
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Publication number: 20130208403Abstract: A capacitor structure includes a storage node; a capacitor dielectric on the storage node; and a plate electrode on the capacitor dielectric. The capacitor dielectric may include a Si-doped ZrO2 layer or crystalline ZrSiOx with a Si/(Zr+Si) content ranging between 4-9% by atomic ratio. The capacitor structure further includes an interfacial TiO2/TiON layer between the storage node and the capacitor dielectric.Type: ApplicationFiled: February 10, 2012Publication date: August 15, 2013Inventors: Noel Rocklein, Vishwanath Bhat, Chris Carlson
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Patent number: 8497566Abstract: A method of forming a capacitor includes forming a conductive first capacitor electrode material comprising TiN over a substrate. TiN of the TiN-comprising material is oxidized effective to form conductive TiOxNy having resistivity no greater than 1 ohm·cm over the TiN-comprising material where x is greater than 0 and y is from 0 to 1.4. A capacitor dielectric is formed over the conductive TiOxNy. Conductive second capacitor electrode material is formed over the capacitor dielectric. Other aspects and implementations are contemplated, including capacitors independent of method of fabrication.Type: GrantFiled: December 28, 2011Date of Patent: July 30, 2013Assignee: Micron Technology, Inc.Inventors: Vishwanath Bhat, Noel Rocklein, F. Daniel Gealy
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Patent number: 8450173Abstract: Electrical components for microelectronic devices and methods for forming electrical components. One particular embodiment of such a method comprises depositing an underlying layer onto a workpiece, and forming a conductive layer on the underlying layer. The method can continue by disposing a dielectric layer on the conductive layer. The underlying layer is a material that causes the dielectric layer to have a higher dielectric constant than without the underlying layer being present under the conductive layer. For example, the underlying layer can impart a structure or another property to the film stack that causes an otherwise amorphous dielectric layer to crystallize without having to undergo a separate high temperature annealing process after disposing the dielectric layer onto the conductive layer. Several examples of this method are expected to be very useful for forming dielectric layers with high dielectric constants because they avoid using a separate high temperature annealing process.Type: GrantFiled: June 28, 2011Date of Patent: May 28, 2013Assignee: Micron Technology, Inc.Inventors: Rishikesh Krishnan, Daniel Gealy, Vidya Srividya, Noel Rocklein
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Publication number: 20130109147Abstract: Some embodiments include methods of forming memory cells. Metal oxide may be deposited over a first electrode, with the deposited metal oxide having a relatively low degree of crystallinity. The degree of crystallinity within the metal oxide may be increased after the deposition of the metal oxide. A dielectric material may be formed over the metal oxide, and a second electrode may be formed over the dielectric material. The degree of crystallinity may be increased with a thermal treatment. The thermal treatment may be conducted before, during, and/or after formation of the dielectric material.Type: ApplicationFiled: October 26, 2011Publication date: May 2, 2013Applicant: MICRON TECHNOLOGY, INC.Inventors: Noel Rocklein, D.V. Nirmal Ramaswamy, Dale W. Collins, Swapnil Lengade, Srividya Krishnamurthy, Mark Korber
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Publication number: 20120320494Abstract: Capacitors and methods of forming capacitors are disclosed, and which include an inner conductive metal capacitor electrode and an outer conductive metal capacitor electrode. A capacitor dielectric region is received between the inner and the outer conductive metal capacitor electrodes and has a thickness no greater than 150 Angstroms. Various combinations of materials of thicknesses and relationships relative one another are disclosed which enables and results in the dielectric region having a dielectric constant k of at least 35 yet leakage current no greater than 1×10?7 amps/cm2 at from ?1.1V to +1.1V.Type: ApplicationFiled: August 29, 2012Publication date: December 20, 2012Applicant: Micron Technology, Inc.Inventors: Rishikesh Krishnan, John Smythe, Vishwanath Bhat, Noel Rocklein, Bhaskar Srinivasan, Jeff Hull, Chris Carlson
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Patent number: 8310807Abstract: Capacitors and methods of forming capacitors are disclosed, and which include an inner conductive metal capacitor electrode and an outer conductive metal capacitor electrode. A capacitor dielectric region is received between the inner and the outer conductive metal capacitor electrodes and has a thickness no greater than 150 Angstroms. Various combinations of materials of thicknesses and relationships relative one another are disclosed which enables and results in the dielectric region having a dielectric constant k of at least 35 yet leakage current no greater than 1×10?7 amps/cm2 at from ?1.1V to +1.1V.Type: GrantFiled: June 12, 2009Date of Patent: November 13, 2012Assignee: Micron Technology, Inc.Inventors: Rishikesh Krishnan, John Smythe, Vishwanath Bhat, Noel Rocklein, Bhaskar Srinivasan, Jeff Hull, Chris Carlson
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Publication number: 20120282754Abstract: Capacitors and methods of forming capacitors are disclosed, and which include an inner conductive metal capacitor electrode and an outer conductive metal capacitor electrode. A capacitor dielectric region is received between the inner and the outer conductive metal capacitor electrodes and has a thickness no greater than 150 Angstroms. Various combinations of materials of thicknesses and relationships relative one another are disclosed which enables and results in the dielectric region having a dielectric constant k of at least 35 yet leakage current no greater than 1×10?7 amps/cm2 at from ?1.1V to +1.1V.Type: ApplicationFiled: July 16, 2012Publication date: November 8, 2012Applicant: MICRON TECHNOLOGY, INC.Inventors: Rishikesh Krishnan, John Smythe, Vishwanath Bhat, Noel Rocklein, Bhaskar Srinivasan, Jeff Hull, Chris Carlson
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Patent number: 8299462Abstract: The invention includes a dielectric mode from ALD-type methods in which two or more different precursors are utilized with one or more reactants to form the dielectric material. In particular aspects, the precursors are aluminum and hafnium and/or zirconium for materials made from a hafnium precursor, the hafnium oxide is predominantly in a tetragonal crystalline phase.Type: GrantFiled: October 25, 2011Date of Patent: October 30, 2012Assignee: Round Rock Research, LLCInventors: Cancheepuram V. Srividya, Noel Rocklein, John Vernon, Jeff Nelson, F. Daniel Gealy, David Korn
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Publication number: 20120241865Abstract: One aspect of the present invention provides an integrated circuit structure including a semiconductor substrate, a bottom dielectric layer positioned on the substrate, at least two capping dielectric layers positioned on the bottom dielectric layer, and a metal layer positioned on the at least two capping dielectric layers, wherein one of the two capping dielectric layers is an aluminum oxide layer, and the other is a silicon oxide layer. Another aspect of the present invention provides an integrated circuit structure including a bottom electrode, a bottom dielectric layer positioned on the bottom electrode, at least two capping dielectric layers positioned on the bottom dielectric layer, and a top electrode positioned on the at least two capping dielectric layers, wherein one of the two capping dielectric layers is an aluminum oxide layer, and the other is a silicon oxide layer.Type: ApplicationFiled: March 21, 2011Publication date: September 27, 2012Applicant: NANYA TECHNOLOGY CORPORATIONInventors: Vassil Antonov, Vishwanath Bhat, Noel Rocklein, Chris Carlson
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Publication number: 20120220098Abstract: Some embodiments include dielectric structures. The structures include first and second portions that are directly against one another. The first portion may contain a homogeneous mixture of a first phase and a second phase. The first phase may have a dielectric constant of greater than or equal to 25, and the second phase may have a dielectric constant of less than or equal to 20. The second portion may be entirely a single composition having a dielectric constant of greater than or equal to 25. Some embodiments include electrical components, such as capacitors and transistors, containing dielectric structures of the type described above. Some embodiments include methods of forming dielectric structures, and some embodiments include methods of forming electrical components.Type: ApplicationFiled: May 1, 2012Publication date: August 30, 2012Applicant: MICRON TECHNOLOGY, INC.Inventors: Noel Rocklein, Chris M. Carlson, Dave Peterson, Cunyu Yang, Praveen Vaidyanathan, Vishwanath Bhat
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Publication number: 20120202358Abstract: Graded dielectric layers and methods of fabricating such dielectric layers provide dielectrics in a variety of electronic structures for use in a wide range of electronic devices and systems. In an embodiment, a dielectric layer is graded with respect to a doping profile across the dielectric layer. In an embodiment, a dielectric layer is graded with respect to a crystalline structure profile across the dielectric layer. In an embodiment, a dielectric layer is formed by atomic layer deposition incorporating sequencing techniques to generate a doped dielectric material.Type: ApplicationFiled: February 3, 2012Publication date: August 9, 2012Inventors: Dan Gealy, Vishwanath Bhat, Cancheepuram V. Srividya, M. Noel Rocklein
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Patent number: 8236372Abstract: Capacitors and methods of forming capacitors are disclosed, and which include an inner conductive metal capacitor electrode and an outer conductive metal capacitor electrode. A capacitor dielectric region is received between the inner and the outer conductive metal capacitor electrodes and has a thickness no greater than 150 Angstroms. Various combinations of materials of thicknesses and relationships relative one another are disclosed which enables and results in the dielectric region having a dielectric constant k of at least 35 yet leakage current no greater than 1×10?7 amps/cm2 at from ?1.1V to +1.1V.Type: GrantFiled: June 12, 2009Date of Patent: August 7, 2012Assignee: Micron Technology, Inc.Inventors: Rishikesh Krishnan, John Smythe, Vishwanath Bhat, Noel Rocklein, Bhaskar Srinivasan, Jeff Hall, Chris Carlson
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Patent number: 8187933Abstract: Some embodiments include dielectric structures. The structures include first and second portions that are directly against one another. The first portion may contain a homogeneous mixture of a first phase and a second phase. The first phase may have a dielectric constant of greater than or equal to 25, and the second phase may have a dielectric constant of less than or equal to 20. The second portion may be entirely a single composition having a dielectric constant of greater than or equal to 25. Some embodiments include electrical components, such as capacitors and transistors, containing dielectric structures of the type described above. Some embodiments include methods of forming dielectric structures, and some embodiments include methods of forming electrical components.Type: GrantFiled: September 30, 2010Date of Patent: May 29, 2012Assignee: Micron Technology, Inc.Inventors: Noel Rocklein, Chris Carlson, Dave Peterson, Cunyu Yang, Praveen Vaidyanathan, Vishwanath Bhat