Abstract: Systems, methods, apparatus, and techniques are provided for decoding data. A plurality of codewords are received in a first order, the first order different from a second order in which the plurality of codewords was encoded, a CRC check is initiated in the first order on each of the plurality of codewords to produce a respective plurality of codeword-level CRC values, the plurality of codeword-level CRC values is combined to produce an overall CRC sequence, and it is determined if there is an error in the plurality of codewords based on the overall CRC sequence.

Abstract: A method includes receiving a codeword over a communications channel and initializing a test codeword to be equal to the codeword received over the communications channel. The method includes performing, for each row of a low-density parity check (LDPC) matrix, an LDPC processing operation on the test codeword. The method includes, once the LDPC processing operations have been performed for all of the rows of the LDPC matrix, repeating the LDPC processing operations. The method includes monitoring progress of the LDPC processing operations. The method includes selectively generating a termination signal in response to the test codeword being a valid codeword according to the LDPC matrix. The method includes terminating the LDPC processing operations in response to generation of the termination signal.

Abstract: Systems and methods are provided for evaluating an asymmetry metric. A receiver receives a synchronization signal, a filtered signal, and a reference signal. A processor processes the synchronization signal and the reference signal to obtain a peak indicator signal, identifies a first set of values and a second set of values from the filtered signal based at least in part on the peak indicator signal, and evaluates an asymmetry metric from the first set of values and the second set of values.

Abstract: The present disclosure includes systems and techniques relating to decoding signals produced within a storage device. A described technique includes retrieving a first codeword from a storage medium, decoding the first codeword, performing a retry process when the decoding was not successful, and retrieving one or more second codewords from the storage medium during the retry process to at least maintain a drive throughput. The retry process can include identifying one or more data chunks within the first codeword having potential defects, generating an erasure mask based on the one or more data chunks, applying, based on a window, one or more erasures within one or more different regions of the first codeword based on one or more corresponding regions of the erasure mask to produce one or more versions of the first codeword, and decoding the one or more versions of the first codeword.

Abstract: Systems and methods are provided for improved designs and performance for iterative decoder systems. In some embodiments, the iterative decoder may be decoupled from FIR samples through an FIR RAM, thus resulting in a less complex design and shorter processing times. In some embodiments, an intermediate memory may be used when passing information between the SOVA and LDPC of the iterative decoder. In some embodiments, the SOVA-required information may be continuously serialized from information received from the LDPC during each LDPC iteration. In some embodiments, the 1/(1+D2) precoder of the HR RLL encoder may be split into two serial, 1/(1+D) precoders. One 1/(1+D) precoder may be pulled outside of the HR RLL encoder and used in conjunction with the iterative decoder. A 1/(1+D) precoder may be used with the iterative decoder while maintaining the RLL constraints imposed upon the encoded information by the HR RLL encoder.

Abstract: A non-linear detector for detecting signals with signal-dependent noise is disclosed. The detector may choose a data sequence that maximizes the conditional probability of detecting the channel data. Since the channel may be time-varying and the precise channel characteristics may be unknown, the detector may adapt one or more branch metric parameters before sending the parameters to a loading block. In the loading block, the branch metric parameters may be normalized and part of the branch metric may be pre-computed to reduce the complexity of the detector. The loading block may then provide the branch metric parameters and any pre-computation to the detector. The detector may then calculate the branch metric associated with the input signal and output the channel data.

Abstract: A system including a first filter module configured to receive an input signal including (i) a first shift in a DC level of the input signal and (ii) a second shift in the DC level of the input signal. The first shift has (i) a first magnitude and (ii) a first duration. The second shift has (i) a second magnitude and (ii) a second duration. The second magnitude is different than the first magnitude. The second duration is greater than the first duration. The first filter module is configured to pass the first shift. The second filter module is configured to detect one or more of (i) the first shift and (ii) the second shift, and in response to detecting one or more of (i) the first shift and (ii) the second shift, filter one or more of (i) the first shift and (ii) the second shift.

Abstract: Systems and methods for storing data on a storage device are disclosed. Data for storage to one of a plurality of tracks of the storage device is received. Each of the plurality of tracks includes a plurality of sectors. The received data is encoded using a track level code. The track level code encodes multiple of the plurality of sectors of the one of the plurality of tracks. The encoded data is stored to the one of the plurality of tracks of the storage device.

Abstract: In one embodiment a data decoding apparatus includes first and second decoding blocks configured to decode codeword bits in a first mode determined by a first probability of non-standard errors and a second mode determined by a second probability of non-standard errors. The apparatus also includes a mode modification logic configured to cause at least one of the first and second decoding blocks to operate in the second mode when the first and second decoding blocks fail to decode the codeword bits in the first mode. In another embodiment, a method includes decoding codeword bits in a first mode determined by a first probability of non-standard errors. When decoding the codeword bits in the first mode fails to decode the codeword bits, the codeword bits are decoded in a second mode determined by a second probability of non-standard errors.

Abstract: The present disclosure relates generally to data decoding, and more particularly to non-binary iterative decoders. Non-binary LDPC codes and LDPC decoders that may be used to decode non-binary LDPC codes are disclosed. Systems and methods are also disclosed that compute messages related to non-binary LDPC codes, in a LLRV form and in a metric vector form and to process these messages in non-binary LDPC decoders. Systems and methods are additionally disclosed that convert messages between the LLRV form and the metric vector form. The implementation and use of non-binary low density parity check code decoders, the computation of messages in the LLRV and metric vector forms, and the use of message conversion systems and methods, according to this disclosure, may provide increased information relating groups of codeword bits, increased computational efficiency, and improved application performance.

Abstract: A transceiver includes a transmitter and a receiver. The transmitter includes an ECC encoder and a data frame generator. The ECC encoder is configured to generate an ECC parity from user data and at least one bit from a syncmark. The data frame generator is configured to generate a data frame for transmission from the syncmark, the user data, and the ECC parity. The receiver includes a detector, an inverter, and a decoder. The detector is configured to detect a received syncmark in a received data frame. The received data frame includes the received syncmark, received user data, and received ECC parity. The inverter is configured to selectively invert a sequence. The sequence includes the received user data, the received ECC parity, and at least one bit from the received syncmark. The decoder is configured to decode one of the sequence or the inverted sequence.

Abstract: Systems, methods, and other embodiments associated with decoding codewords are described. According to one embodiment, a read channel includes a set of memories and a decoding logic. The set of memories is configured to decode a plurality codewords. At least one memory is classified as an inactive memory for use when a failure occurs. The remaining memories of the set of memories are classified as active memory for decoding. The decoding logic is configured to decode the plurality of codewords using the active memory of the set of memories. When the decoding logic fails to decode a codeword, which is stored in a memory of the active memory, resulting in a failed codeword, the memory of the active memory is reclassified as a memory of the inactive memory.

Abstract: The present disclosure includes apparatus, systems and techniques relating to iterative decoder memory arrangement. A described apparatus includes R banks; Q banks; circuitry configured to store R data for a current codeword in a first R bank of the R banks and store R data for a previous codeword in a second R bank of the R banks; circuitry configured to alternate among the R banks for storing current codeword R data; circuitry configured to store Q data for the current codeword in a first Q bank of the Q banks and store Q data for the previous codeword in a second Q bank of the Q banks; and circuitry configured to alternate among the Q banks for storing current codeword Q data. The apparatus can include circuitry configured to interleave read accesses among the R banks.

Abstract: Systems and methods are provided that use LDPC codes to determine the locations of insertions or deletions within bit-strings of information transmitted through communication channels and which notify a LDPC decoder of the locations of the insertions or deletions prior to the start of the decoding process. The use of such systems and methods, according to this disclosure, may improve LDPC decoder performance by reducing errors cause by insertions and/or deletions. The use of such systems and methods, according to this disclosure, may also provide improved application performance and larger data transmission rates.

Abstract: A decoder for a communication system includes a channel detection module configured to receive initial estimates of respective code words, wherein the initial estimates of the respective code words correspond to a signal received via a communication channel, arrange the initial estimates of the respective code words into a plurality of groups, and generate probability information associated with selected data bits of the respective code words in the plurality of groups, wherein the probability information indicates probabilities of decoding decisions of the selected data bits. A computation module is configured to generate bit estimations for each of the selected data bits based on the probability information and feedback information. A decoding module is configured to selectively generate, the feedback information and an estimate signal corresponding to the respective code words.

Abstract: A system including an input configured to receive data and an encoder module configured to perform an encoding operation on the data using an error correcting code. The data comprises one or more bits inserted at predetermined locations in the data. A number of the one or more bits inserted in the data corresponds to a number of inner-code parity bits to be inserted at the predetermined locations subsequent to the encoding operation being performed on the data. The encoder module is configured to use, subsequent to the encoding operation being performed on the data, an inner code to generate the inner-code parity bits based on the data, and at the predetermined locations in the data, replace the one or more bits inserted in the data with the inner-code parity bits generated based on use of the inner code.

Abstract: A system including a padding field generator and an encoder. The padding field generator is configured to generate a first padding field for a frame. The frame includes (i) a preamble field, (ii) a syncmark field, and (iii) a data field. The first padding field is located between (i) the preamble field and (ii) the syncmark field. The preamble field, the first padding field, and the syncmark field precede the data field. The encoder is configured to encode, using an error-correcting code, (i) the first padding field, (ii) the syncmark field, and (iii) the data field; and to generate, based on the encoding performed using the error-correcting code, one or more parity bits. The one or more parity bits are stored in a parity field of the frame. The parity field is located subsequent to the data field in the frame.

Abstract: Apparatuses and methods associated with instant syndrome computation in a layered LDPC decoder are described. According to one embodiment, an apparatus includes a plurality of hardware layers, where a hardware layer is configured to compute a syndrome value from one or more bit values in the codeword. The apparatus includes a plurality of physical memories configured to store a plurality of syndrome values, where a physical memory is configured to store syndrome values computed by one or more hardware layers. The apparatus includes circuitry configured to simultaneously store a syndrome value computed by a hardware layer in physical memories associated with a bit in the codeword. The apparatus includes a decode logic configured to signal successful decoding of the codeword based, at least in part, on determining that a set of syndromes are satisfied based on values stored in the plurality of physical memories.

Abstract: In iterative decoding, a data recovery scheme corrects for corrupted or defective data by determining reliability metrics for blocks of decoded data. Block or windowed detectors generate block reliability metrics for data blocks (rather than individual bits) of decoded data using soft information from the regular decoding mode or from new iterative decoding iterations performed during error recovery mode. An error recovery system triggers corrective decoding of selected data blocks based on the block reliability metrics, by for example, comparing the block reliability metrics to a threshold or by selecting an adjustable number of the least reliable data blocks.

Abstract: Systems and methods are provided for improved designs and performance for iterative decoder systems. In some embodiments, the iterative decoder may be decoupled from FIR samples through an FIR RAM, thus resulting in a less complex design and shorter processing times. In some embodiments, an intermediate memory may be used when passing information between the SOVA and LDPC of the iterative decoder. In some embodiments, the SOVA-required information may be continuously serialized from information received from the LDPC during each LDPC iteration. In some embodiments, the 1/(1+D2) precoder of the HR RLL encoder may be split into two serial, 1/(1+D) precoders. One 1/(1+D) precoder may be pulled outside of the HR RLL encoder and used in conjunction with the iterative decoder. A 1/(1+D) precoder that may be used with the iterative decoder while maintaining the RLL constraints imposed upon the encoded information by the HR RLL encoder.