Abstract: A low-density parity check (LDPC) decoder comprises a decoded data stream generator that generates a decoded data stream based on a received data stream and a set of matrix-based codewords. The matrix-based codewords form a LDPC parity check matrix H. A decoder control module at least one of prewrites or replaces a selected portion of at least one of the plurality of codewords with zeros prior to generation of the decoded data stream.

Abstract: A decoder system comprises a tensor-product code (TPC) decoder that decodes a received data stream to generate a decoded signal. A mark module that replaces low-density parity check (LDPC) parity bits of the decoded signal with 0s to generate a reset output signal. A deinterleave module deinterleaves error correction parity bits that are within the reset output signal to generate a deinterleaved signal that comprises a decoded portion and a concatenated portion. The concatenated portion comprises the error correction parity bits. A parity decoder module removes the concatenated portion from the deinterleaved signal.

Abstract: The present disclosure includes apparatus, systems and techniques relating to iterative decoder memory arrangement. In some implementations, an apparatus includes a memory module to communicate with an iterative code decoder. The memory module includes a single R memory component to store R data associated with a current codeword, and R data associated with a previous codeword. The memory module includes a Q memory component to store Q data associated with the current codeword, and Q data associated with the previous codeword. The memory module includes a channel detector memory component to store channel extrinsic information.

Abstract: The disclosed technology provides systems and methods for encoding data based on a run-length-limited code and an error correction code to provide codewords. The codewords include RLL-encoded data that are produced based on the RLL code, and parity information that are produced based on the error correction code. The parity information is interleaved among the RLL-encoded data. In one embodiment, the codeword is produced by separately producing the RLL-encoded data and the parity information, and interleaving the parity information among the RLL-encoded data. In one embodiment, the codeword is produced by producing the RLL-encoded data, and using erasure decoding to compute the parity information.

Abstract: Systems and methods are provided for a quasi-cyclic low-density parity check (QC-LDPC) encoders that have reduced memory requirements. In some embodiments, the LDPC encoder may store a quasi-cyclic parity seed matrix instead of a full code generator matrix. The LDPC encoder may receive a plurality of user symbols and compute a parity seed vector based at least in part on the received user symbols. The LDPC encoder may then use the quasi-cyclic parity seed matrix and the parity seed vector to generate a plurality of parity symbols for the user symbols. In some embodiments, the LDPC encoder may generate a full code generator matrix from a quasi-cyclic parity seed matrix instead of storing the full code generator matrix.

Abstract: A decoding system for a communication channel includes N parallel channel detection modules that generate N first probability vectors based on sequences of X correlated bits in each of N groups of correlated bits, respectively. N parallel updating modules generate M second probability vectors based on the N first probability vectors and N feedback signals. N parallel estimation modules generate estimates of the X correlated bits in each of the N groups of correlated bits based on the M second probability vectors. N parallel decoding modules generate the N feedback signals and N output signals based on the estimates of the X correlated bits in each of the N groups of correlated bits. X is an integer greater than one, M is an integer greater than or equal to one, and N is an integer greater than or equal to M.

Abstract: Systems and methods are provided that use LDPC codes to determine the locations of insertions or deletions within bit-strings of information transmitted through communication channels and which notify a LDPC decoder of the locations of the insertions or deletions prior to the start of the decoding process. The use of such systems and methods, according to this disclosure, may improve LDPC decoder performance by reducing errors cause by insertions and/or deletions. The use of such systems and methods, according to this disclosure, may also provide improved application performance and larger data transmission rates.

Abstract: A non-linear detector for detecting signals with signal-dependent noise is disclosed. The detector may choose a data sequence that maximizes the conditional probability of detecting the channel data. Since the channel may be time-varying and the precise channel characteristics may be unknown, the detector may adapt one or more branch metric parameters before sending the parameters to a loading block. In the loading block, the branch metric parameters may be normalized and part of the branch metric may be pre-computed to reduce the complexity of the detector. The loading block may then provide the branch metric parameters and any pre-computation to the detector. The detector may then calculate the branch metric associated with the input signal and output the channel data.

Abstract: A decoder memory system comprises a first memory comprising at least a portion of a parity check matrix H. A second memory receives the portion from the first memory and that is associated with a previous decoding iteration. A third memory communicates with the first memory, receives the parity check matrix H and is associated with a current decoding iteration. A fourth memory comprises likelihood ratios. A control module generates a LDPC decoded signal based on the parity check matrix H, the previous decoded iteration and the likelihood ratios.

Abstract: Methods and apparatus are provided for processing a plurality of data blocks. In accordance with embodiments of the invention, a correction flag for each of the data blocks can be received, along with information on at least one error event for each of the data blocks. Using this received information, a search trellis corresponding to the data blocks can be determined. Determining the search trellis can include determining a plurality of branches and computing a branch metric for each of the branches. A search on the search trellis can be performed to identify at most one error event for each data block, where the search is based on the branch metrics.

Abstract: A coding system for digital data. The coding system includes a constrained encoder module configured to generate encoded data based on a first constrained code; a bit insertion module configured to insert at least one bit location in the encoded data; and an inner encoding module configured to (i) generate inner-code parity bits based on the encoded data, and (ii) program the inner-code parity bits into the at least one bit location.

Abstract: Systems and methods are provided for encoding a stream of datawords based on a tensor product code to provide a stream of codewords, and detecting and decoding a stream of received data based on a tensor product code to provide a decoded stream of data. In one aspect, the tensor product code is based on two codes including an inner code and an outer parity hiding code, where the outer parity hiding code is an iterative code. In certain embodiments, the outer parity hiding code is a Turbo code or a low density parity check (LDPC) code.

Abstract: A system and method of adapting a FIR filter with a mixed minimum-mean-square-error/zero-forcing adaptation is disclosed. A channel response module attempts to approximate a noiseless component of the channel response. The output of the channel response module is utilized to adapt a FIR filter module. In some embodiments, a combination of the output of the channel module and the noiseless channel output is utilized to adapt the FIR filter. In some embodiments, a second FIR filter module is utilized to process the noiseless channel output, which is then compared to the target response to generate an error signal, which may be used to adapt both the first and second FIR filter modules.

Abstract: Systems and methods are provided for encoding and decoding constrained codewords using an enumerative coding graph. The constrained codewords may contain run-length and DC level limits. The enumerative coding graph contains a series of states and each state has multiple branches that lead to other states. Each state in the enumerative coding graph is associated with at least two bits of an enumerative codeword. Configuring the structure of the graph and cardinalities associated with each state allows the encoder to generate a code that conforms to defined constraints.

Abstract: A high-rate constrained code is provided to encode/decode channel data. A transformer translates binary channel data into an arbitrary alphabet size. The transformer selects an indicator word and makes forbidden prefix substitutions in the data to be transformed. A finite-state encoder imposes some user-defined constraint on the transformed data before the data is transferred to the channel. The high-rate constrained coding technique may be used to produce high-rate DC-limited and run-length-limited codes. The high-rate code can be used in tandem with error-correcting codes.

Abstract: The present disclosure relates generally to data decoding, and more particularly to non-binary iterative decoders. Non-binary LDPC codes and LDPC decoders that may be used to decode non-binary LDPC codes are disclosed. Systems and methods are also disclosed that compute messages related to non-binary LDPC codes, in a LLRV form and in a metric vector form and to process these messages in non-binary LDPC decoders. Systems and methods are additionally disclosed that convert messages between the LLRV form and the metric vector form. The implementation and use of non-binary low density parity check code decoders, the computation of messages in the LLRV and metric vector forms, and the use of message conversion systems and methods, according to this disclosure, may provide increased information relating groups of codeword bits, increased computational efficiency, and improved application performance.

Abstract: An encoder system includes a receive module that receives a data stream. A parity generation module generates parity bits based on the data stream and a tensor-product code. A parity insertion module combines the parity bits and the data stream to generate encoded bits.

Abstract: The disclosed technology provides systems and methods for encoding data based on a run-length-limited code and an error correction code to provide codewords. The codewords include RLL-encoded data that are produced based on the RLL code, and parity information that are produced based on the error correction code. The parity information is interleaved among the RLL-encoded data. In one embodiment, the codeword is produced by separately producing the RLL-encoded data and the parity information, and interleaving the parity information among the RLL-encoded data. In one embodiment, the codeword is produced by producing the RLL-encoded data, and using erasure decoding to compute the parity information.

Abstract: Embodiments of the present invention provide methods and systems for decoding information in a communications system with an improved bit error rate. Correlated groups of bits are grouped, and joint information of the correlated bit groups is made available to the decoder. The decoder takes advantage of the joint information to improve the error rate.

Abstract: In a device having a data channel, in which random numbers are needed, such as a data storage device that uses random numbers to generate keys for cryptographic applications, random numbers are generated by a deterministic random bit generator seeded by bits derived from noise on the channel itself. The bits may be extracted from the least significant bits of the data signal after it is digitized, because those bits correspond to the noise in the signal. The extraction may occur immediately after digitization, or after subsequent filtering. A data signal emulator may be provided to simulate a data signal if a seed is required at a time when there is no data activity on the channel. The extracted bits may be post-processed to remove bias before the seed is provided to the deterministic random bit generator.