Abstract: A system including a first filter module and a second filter module. The first filter module is configured to (i) pass a first DC shift in an input signal and (ii) convert a second DC shift in the input signal to a first component and a second component. The first DC shift is shorter in duration than the second DC shift. The second filter module is configured to detect one or more of (i) the first DC shift and (ii) the first component and the second component of the second DC shift. In response to detecting one or more of (i) the first DC shift and (ii) the first component and the second component of the second DC shift, the second filter module is configured to filter one or more of (i) the first DC shift and (ii) the first component and the second component of the second DC shift.

Abstract: A decoding system including a low density parity check (LDPC) processing module and a termination module. The LDPC processing module is configured to receive a test codeword based on a codeword received over a communications channel, and perform, for each row of a parity check matrix, a processing operation on the test codeword. The LDPC processing module is configured to, once the processing operations have been performed for all the rows, repeat the processing operations. The termination module is configured to monitor progress of the LDPC processing module and selectively generate a termination signal in response to the test codeword being a valid codeword according to the parity check matrix. The LDPC processing module is further configured to terminate the processing operations in response to generation of the termination signal.

Abstract: Systems and methods are provided for improved designs and performance for iterative decoder systems. In some embodiments, the iterative decoder may be decoupled from FIR samples through an FIR RAM, thus resulting in a less complex design and shorter processing times. In some embodiments, an intermediate memory may be used when passing information between the SOVA and LDPC of the iterative decoder. In some embodiments, the SOVA-required information may be continuously serialized from information received from the LDPC during each LDPC iteration. In some embodiments, the 1/(1+D2) precoder of the HR RLL encoder may be split into two serial, 1/(1+D) precoders. One 1/(1+D) precoder may be pulled outside of the HR RLL encoder and used in conjunction with the iterative decoder. A 1/(1+D) precoder may be used with the iterative decoder while maintaining the RLL constraints imposed upon the encoded information by the HR RLL encoder.

Abstract: Encoder and decoder apparatus and methods derive a plurality of parity bits from a single codeword. Encoder apparatus may include a receive module receiving a data stream, a parity generation module generating a plurality of parity bits based on the data stream and a word of a tensor-product code, and a parity insertion module combining the plurality of parity bits and the data stream to generate encoded bits. Decoder apparatus may include a detector receiving and outputting encoded data, a first decoder generating first log-likelihood ratios (LLRs) from the encoded data, an error recovery module generating second LLRs from the encoded data, a second decoder that derives syndrome data from the first and second LLRs, a post-processor that combines data from the first decoder with error events from the error recovery module to generate corrected data, the post-processor further identifying a plurality of parity bits in the corrected data.

Abstract: Systems and methods of reading data from a storage device are provided. A first codeword and a second codeword are read from a storage device, where the second codeword is positioned after the first codeword. The first and second codewords are decoded in parallel, and the decoding of the second codeword completes before the decoding of the first codeword completes. The decoded second codeword and a signal indicating whether the decoding of the second codeword is complete are transmitted to control circuitry before the decoding of the first codeword completes.

Abstract: Methods and apparatus are provided for processing a plurality of data blocks. In accordance with embodiments of the invention, a correction flag for each of the data blocks can be received, along with information on at least one error event for each of the data blocks. Using this received information, a search trellis corresponding to the data blocks can be determined. Determining the search trellis can include determining a plurality of branches and computing a branch metric for each of the branches. A search on the search trellis can be performed to identify at most one error event for each data block, where the search is based on the branch metrics.

Abstract: A communication system includes an encoder configured to encode first data words to generate code words. A modulator is configured to modulate the code words into a first signal that is transmitted on a communication channel. A demodulator is configured to demodulate a second signal, received from the communication channel, into estimates of the code words. The second signal is based on the first signal. A decoding module is configured to group the estimates of the code words into a plurality of groups of correlated data bits, wherein the correlated data bits include statistical relationships between different data bits, generate a plurality of group estimate signals each corresponding to a respective one of the plurality of groups of correlated data bits, and generate, by combining the plurality of group estimate signals, an estimate signal corresponding to the first data words.

Abstract: A coding system for digital data. The coding system includes a constrained encoder module configured to generate encoded data based on a first constrained code; a bit insertion module configured to insert at least one bit location in the encoded data; and an inner encoding module configured to (i) generate inner-code parity bits based on the encoded data, and (ii) program the inner-code parity bits into the at least one bit location.

Abstract: Systems and methods are provided for improved designs and performance for iterative decoder systems. In some embodiments, the iterative decoder may be decoupled from FIR samples through an FIR RAM, thus resulting in a less complex design and shorter processing times. In some embodiments, an intermediate memory may be used when passing information between the SOVA and LDPC of the iterative decoder. In some embodiments, the SOVA-required information may be continuously serialized from information received from the LDPC during each LDPC iteration. In some embodiments, the 1/(1+D2) precoder of the HR RLL encoder may be split into two serial, 1/(1+D) precoders. One 1/(1+D) precoder may be pulled outside of the HR RLL encoder and used in conjunction with the iterative decoder. A 1/(1+D) precoder that may be used with the iterative decoder while maintaining the RLL constraints imposed upon the encoded information by the HR RLL encoder.

Abstract: The present disclosure includes apparatus, systems and techniques relating to iterative decoder memory arrangement. A described apparatus includes a single R memory component including R banks, a Q memory component including Q banks, a channel detector memory component to store channel extrinsic information associated with current and previous codewords, and an iterative decoder communicatively coupled with the single R memory component, the Q memory component, and the channel detector memory component. The apparatus can be configured to alternate among the R banks for storing R data associated with a current codeword. The apparatus can be configured to alternate among the Q banks for storing Q data associated with a current codeword.

Abstract: Systems and methods are provided for decoding a vector from a communications channel using a non-binary decoder. The communications channel may correspond to a wired or wireless channel. A message passing process computes R messages corresponding to a variable node of the non-binary decoder. Decoder extrinsic information is formed for the variable node by combining the R messages. The decoder extrinsic information is provided to a soft-detector.

Abstract: Systems, methods, and other embodiments associated with an encoder. In one embodiment, a system includes an encoder having a code word generator and an appending logic. The code word generator is configured to generate code words based on input data and identify one or more short code words. A short code word has a length less than a length of a full code word. The appending logic is configured to append at least one dummy value to at least one of the short code words to convert the at least one short code word to a full code word. The encoder may further be configured to encode the converted full code word and store the converted full code word without the at least one dummy value in a storage medium.

Abstract: The disclosed technology provides systems and methods for encoding data based on a run-length-limited code and an error correction code to provide codewords. The codewords include RLL-encoded data that are produced based on the RLL code, and parity information that are produced based on the error correction code. The parity information is interleaved among the RLL-encoded data. In one embodiment, the codeword is produced by separately producing the RLL-encoded data and the parity information, and interleaving the parity information among the RLL-encoded data. In one embodiment, the codeword is produced by producing the RLL-encoded data, and using erasure decoding to compute the parity information.

Abstract: Methods and systems are disclosed herein for generating parity information for using information in a low-density parity check (LDPC) encoder. A quasi-cyclic LDPC generator matrix K can be generated based on the non-invertible parity-check matrix H. Parity information can be generated by the LDPC encoder based at least in part on the user information, the non-invertible parity check matrix H, and the quasi-cyclic LDPC generator matrix K.

Abstract: A non-linear detector for detecting signals with signal-dependent noise is disclosed. The detector may choose a data sequence that maximizes the conditional probability of detecting the channel data. Since the channel may be time-varying and the precise channel characteristics may be unknown, the detector may adapt one or more branch metric parameters before sending the parameters to a loading block. In the loading block, the branch metric parameters may be normalized and part of the branch metric may be pre-computed to reduce the complexity of the detector. The loading block may then provide the branch metric parameters and any pre-computation to the detector. The detector may then calculate the branch metric associated with the input signal and output the channel data.

Abstract: Encoder and decoder apparatus and methods derive a plurality of parity bits from a single codeword. Encoder apparatus may include a receive module receiving a data stream, a parity generation module generating a plurality of parity bits based on the data stream and a word of a tensor-product code, and a parity insertion module combining the plurality of parity bits and the data stream to generate encoded bits. Decoder apparatus may include a detector receiving and outputting encoded data, a first decoder generating first log-likelihood ratios (LLRs) from the encoded data, an error recovery module generating second LLRs from the encoded data, a second decoder that derives syndrome data from the first and second LLRs, a post-processor that combines data from the first decoder with error events from the error recovery module to generate corrected data, the post-processor further identifying a plurality of parity bits in the corrected data.

Abstract: A system includes a first channel detection module configured to receive a first channel estimate including a plurality of correlated data bits from a communication channel. The correlated data bits include statistical relationships between different data bits based on the statistical relationships, group together the plurality of correlated data bits, and generate a first probability vector based on the correlated data bits as grouped together. The first probability vector includes probabilities that each of the correlated data bits has a respective value. A computation module is configured to generate bit estimations based on the first probability vector. A decoding module is configured to, based on the bit estimations, selectively generate an output signal corresponding to the bit estimations, and selectively generate a feedback signal. The computation module is further configured to generate the bit estimations based on the feedback signal.

Abstract: Systems and methods are provided for improved designs and performance for iterative decoder systems. In some embodiments, the iterative decoder may be decoupled from FIR samples through an FIR RAM, thus resulting in a less complex design and shorter processing times. In some embodiments, an intermediate memory may be used when passing information between the SOVA and LDPC of the iterative decoder. In some embodiments, the SOVA-required information may be continuously serialized from information received from the LDPC during each LDPC iteration. In some embodiments, the 1/(1+D2) precoder of the HR RLL encoder may be split into two serial, 1/(1+D) precoders. One 1/(1+D) precoder may be pulled outside of the HR RLL encoder and used in conjunction with the iterative decoder. This may allow for a 1/(1+D) precoder that may be used with the iterative decoder while maintaining the RLL constraints imposed upon the encoded information by the HR RLL encoder.

Abstract: The disclosed technology provides systems and methods for encoding data based on a run-length-limited code and an error correction code to provide codewords. The codewords include RLL-encoded data that are produced based on the RLL code, and parity information that are produced based on the error correction code. The parity information is interleaved among the RLL-encoded data. In one embodiment, the codeword is produced by separately producing the RLL-encoded data and the parity information, and interleaving the parity information among the RLL-encoded data. In one embodiment, the codeword is produced by producing the RLL-encoded data, and using erasure decoding to compute the parity information.

Abstract: A non-linear post-processor for estimating at least one source of signal-dependent noise is disclosed. The post processor may receive a set of preliminary decisions from a sub-optimal detector along with the sampled data signal. The post-processor may then compute the transition jitter and white noise associated with each preliminary decision in the set and assign a cost metric to each decision based on the total signal noise. The post-processor may output the decision with the lowest cost metric as the final decision of the detector.