Patents by Inventor Patrick L. Connor

Patrick L. Connor has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7685250
    Abstract: Techniques to pace the transmission of packets to multiple connections using one or more queues or storages. When multiple queues are used, each queue may have an associated throughput rate and each of the queues may have a different associated throughput rate.
    Type: Grant
    Filed: March 9, 2005
    Date of Patent: March 23, 2010
    Assignee: Intel Corporation
    Inventors: Patrick L. Connor, Scott P. Dubal
  • Publication number: 20100030930
    Abstract: A command-response bus protocol reduces the number of response transactions generated on a bus. According to an embodiment, an array of data is divided into a number of packets and transmitted over the bus in respective transactions. The transactions each include a writeback flag, which is enabled for the last packet but otherwise disabled. When a receiver of the packets observes the enabled writeback flag, it generates a response transaction. The response transaction indicates either that all packets of the array were received properly or that the commanded operation has been completed for the entire array. Overall, the number of bus transactions are reduced with respect to alternative schemes that require a response transaction for each transmitted packet.
    Type: Application
    Filed: October 9, 2009
    Publication date: February 4, 2010
    Applicant: INTEL CORPORATION
    Inventor: Patrick L. CONNOR
  • Patent number: 7603491
    Abstract: A command-response bus protocol reduces the number of response transactions generated on a bus. According to an embodiment, an array of data is divided into a number of packets and transmitted over the bus in respective transactions. The transactions each include a writeback flag, which is enabled for the last packet but otherwise disabled. When a receiver of the packets observes the enabled writeback flag, it generates a response transaction. The response transaction indicates either that all packets of the array were received properly or that the commanded operation has been completed for the entire array. Overall, the number of bus transactions are reduced with respect to alternative schemes that require a response transaction for each transmitted packet.
    Type: Grant
    Filed: June 19, 2003
    Date of Patent: October 13, 2009
    Assignee: Intel Corporation
    Inventor: Patrick L. Connor
  • Patent number: 7492913
    Abstract: A directed audio system, a network interface communicatively coupled with a network, and a controller to receive, via the network interface, an estimate for a location from a locating device communicatively coupled with the network, and to cause the directed audio system to direct an audio signal based at least in part on an estimate for the location received from the locating device.
    Type: Grant
    Filed: December 16, 2003
    Date of Patent: February 17, 2009
    Assignee: Intel Corporation
    Inventors: Patrick L. Connor, Douglas D. Boom, Scott P. Dubal, Mark V. Montecalvo
  • Patent number: 7474616
    Abstract: A method, apparatus, and signal-bearing medium for indicating and responding to congestion in a network. When a buffer at a receiver is nearly full, the receiver may send a congestion indication to the sender(s) that is causing the congestion. When the receiver(s) receives the congestion indication, it may implement a flow-control technique to temporarily lower the rate that it is sending the frames to the receiver, and then increase the rate.
    Type: Grant
    Filed: February 19, 2002
    Date of Patent: January 6, 2009
    Assignee: Intel Corporation
    Inventor: Patrick L. Connor
  • Patent number: 7444642
    Abstract: The present disclosure describes a method comprising issuing a plurality of commands to a controller, wherein the commands are issued in a first order, and wherein the completion status of commands is written to the memory in a second order, and wherein the second order may be different from the first order. Also described is an apparatus comprising a controller adapted to accept a plurality of commands, wherein the commands are issued in a first order, and completion status of commands is written to the memory in a second order, and wherein the second order may be different from the first order.
    Type: Grant
    Filed: November 15, 2001
    Date of Patent: October 28, 2008
    Assignee: Intel Corporation
    Inventors: Linden Minnick, Roy Callum, Patrick L. Connor
  • Patent number: 7418716
    Abstract: Provided are a method, apparatus, system, and article of manufacture for interfacing a device to a host, wherein in certain embodiments a device interface in the device receives a request generated by a device driver in the host. The device interface processes the request, wherein a plurality of device interfaces corresponding to a plurality of devices are capable of processing the request. An operation associated with the device is executed, by the device interface, in response to processing the request.
    Type: Grant
    Filed: December 19, 2003
    Date of Patent: August 26, 2008
    Assignee: Intel Corporation
    Inventors: Mark V. Montecalvo, Scott P. Dubal, Patrick L. Connor
  • Patent number: 7415732
    Abstract: A method for preventing counterfeit of a hardware device is disclosed. The method comprises determining whether a first indicator for a hardware device is set, wherein the first indicator when set indicates that the device is not a counterfeit device, and if the first indicator is not set, then activating a counter, setting a second indicator when the counter expires, and operating the hardware device in a counterfeit mode when the second indicator is set, wherein the counterfeit mode identifies the hardware device as a counterfeit device. Other embodiments are also disclosed.
    Type: Grant
    Filed: September 22, 2005
    Date of Patent: August 19, 2008
    Assignee: Intel Corporation
    Inventors: Mark V. Montecalvo, Douglas D. Boom, Elizabeth M. Kappler, Scott P. Dubal, Patrick L. Connor
  • Patent number: 7415513
    Abstract: Provided are a method, apparatus, system, and article of manufacture, wherein in certain embodiments a network adapter having an offload protocol stack receives a query. The offload protocol stack of the network adapter is configured to provide a programmable identity for the offload protocol stack of the network adapter. A response is generated to the query by processing the query in the configured offload protocol stack, wherein the response is based on the programmable identity. The generated response is sent by the network adapter.
    Type: Grant
    Filed: December 19, 2003
    Date of Patent: August 19, 2008
    Assignee: Intel Corporation
    Inventors: Patrick L. Connor, Mark V. Montecalvo, Scott P. Dubal
  • Patent number: 7404040
    Abstract: Packet data received by a network controller is parsed and at least a portion of a received packet is stored by the network controller in both a host memory of a system and also in a cache memory of the central processing unit of the system. Other embodiments are described and claimed.
    Type: Grant
    Filed: December 30, 2004
    Date of Patent: July 22, 2008
    Assignee: Intel Corporation
    Inventors: John Anthony Ronciak, Christopher David Leech, Prafulla Shashikant Deuskar, Jesse C. Brandeburg, Patrick L. Connor
  • Patent number: 7373419
    Abstract: Provided are a method, system, and article of manufacture for managing network throughput. An application identifies at least one network connection of a plurality of network connections, wherein packets arriving via the one network connection require greater resources at a computational device relative to resources required by other network connections. The application determines if resources required at the computational device by the plurality of network connections exceed a threshold and eliminates the at least one network connection to the computational device.
    Type: Grant
    Filed: December 6, 2002
    Date of Patent: May 13, 2008
    Assignee: Intel Corporation
    Inventors: Patrick L. Connor, Eric K. Mann
  • Patent number: 7299350
    Abstract: A system for improved decryption performance includes a computer in electronic communication with an encrypted network. A controller performs a decryption operation on an encrypted packet received from the network, and the computer asserts an interrupt prior to the system completing transfer of the decrypted packet back to host memory to reduce the additional latency a packet suffers during Secondary Use. An additional interrupt may be asserted after the Secondary Use operation is complete, to ensure that the Secondary Use packet is processed. A method for improving decryption performance similarly includes asserting an interrupt prior to the complete transfer of a decrypted packet from a controller back to host memory during Secondary Use. The method may further include asserting an additional interrupt after the Secondary Use operation is complete, to ensure that the Secondary Use packet is processed.
    Type: Grant
    Filed: January 17, 2002
    Date of Patent: November 20, 2007
    Assignee: Intel Corporation
    Inventors: Patrick L Connor, Linden Minnick
  • Patent number: 7286483
    Abstract: End-to-end data transfer between computing platforms in a transport control protocol (TCP) environment is improved by restricting which packets are stored in a receive memory of an input/output (I/O) circuit. In one embodiment, received packets are examined as to type, and the number of packets stored in the receive memory is monitored. If the number of stored packets exceeds a threshold value, then subsequently received data packets are discarded, whereas latency-sensitive priority data such as acknowledgements (ACKs) are retained in the receive memory, until the number of stored packets is reduced. Various methods, as well as application of the circuit to a system and to a machine-readable article, are also described.
    Type: Grant
    Filed: November 14, 2002
    Date of Patent: October 23, 2007
    Assignee: Intel Corporation
    Inventor: Patrick L. Connor
  • Patent number: 7248593
    Abstract: A method, apparatus, and article of manufacture for retaining packet order in multiprocessor systems utilizing multiple transmit queues while minimizing spinlocks are disclosed herein. Embodiments of the present invention define multiple transmit queues for a given priority level of packets to allow parallel processing and queuing of packets having equal priority in different transmit queues. Queuing packets of equal priority in different transmit queues minimizes processor time spent attempting to acquire queue-specific resources associated with one particular transmit queue. In addition, embodiments of the present invention provide an assignment mechanism to maximize utilization of the multiple transmit queues by queuing packets corresponding to each transmit request in a next available transmit queue defined for a given priority level. Coordination between hardware and software allows the order of the queued packets to be maintained in the transmission process.
    Type: Grant
    Filed: May 9, 2002
    Date of Patent: July 24, 2007
    Assignee: Intel Corporation
    Inventors: Linden Minnick, Patrick L. Connor
  • Patent number: 7246038
    Abstract: Provided are a method, system, and article of manufacture, wherein in certain embodiments, an indicator is searched for in a computational platform, and wherein the indicator indicates an operational state of a device coupled to the computational platform. A determination is made that the indicator has been modified to disable the device. The indicator is modified to allow enablement of the disabled device. The device is tested to determine whether the device is capable of operating correctly.
    Type: Grant
    Filed: February 10, 2006
    Date of Patent: July 17, 2007
    Assignee: Intel Corporation
    Inventors: Scott P. Dubal, Patrick L. Connor, Mark V. Montecalvo
  • Patent number: 7181609
    Abstract: A system and method for initialization of a computer system is described. Faster initialization of a computer system is possible by allowing certain device driver initialization tasks to overlap with other initialization and operating system tasks. option-ROMs resident on hardware device drivers define the initialization tasks to be performed prior to device driver initialization. Initial computer code for booting the computing device, such as a BIOS, is executed. As option-ROMs for hardware devices are scanned and executed, specific device initialization information is accessed from the devices and placed in pre-defined buffer areas. These accesses occur in parallel to other start up tasks. When device drivers are loaded, some of their initialization has already completed, thereby shortening the time necessary to boot the system.
    Type: Grant
    Filed: August 15, 2003
    Date of Patent: February 20, 2007
    Assignee: Intel Corporation
    Inventors: Patrick L. Connor, Mark V. Montecalvo, Douglas D. Boom, Scott P. Dubal
  • Patent number: 7177778
    Abstract: Provided is a method and system for managing data processing rates at a network adapter using a temperature sensor. A temperature of a component in the adapter transmitting data over a network is measured. A rate at which data is processed in the adapter over the network is reduced in response to determining that the measured temperature exceeds a threshold.
    Type: Grant
    Filed: November 30, 2004
    Date of Patent: February 13, 2007
    Assignee: Intel Corporation
    Inventors: Daniel R. Gaur, Patrick L. Connor, Scott P. Dubal
  • Patent number: 7177913
    Abstract: Disclosed is a method, system, and program for adding an operation (e.g., an operation that provides information about data for transfer or a storage operation) to a structure (e.g., a queue). If a priority level associated with a data packet identified by the operation has a first designation comprising a high priority, placing the operation into a first structure (e.g., a queue) with a least number of operations. If the priority level associated with the data packet identified by the operation has a second designation comprising a low priority, placing the operation into a second structure (e.g., a queue) with a most number of operations.
    Type: Grant
    Filed: December 5, 2002
    Date of Patent: February 13, 2007
    Assignee: Intel Corporation
    Inventor: Patrick L. Connor
  • Patent number: 7177956
    Abstract: An arrangement is provided for ingress processing optimization via traffic classification and grouping. A plurality of packets are classified according to a classification criterion. The classified packets are used to generate a packet bundle containing packets that are uniform with respect to the classification criterion. The packet bundle and its corresponding packet bundle descriptor are transferred to a host which then processes the packet bundle as a whole according to the information contained in the packet bundle descriptor.
    Type: Grant
    Filed: June 1, 2005
    Date of Patent: February 13, 2007
    Assignee: Intel Corporation
    Inventors: Erik K. Mann, Patrick L. Connor, Diamant Nimrod
  • Patent number: 7164678
    Abstract: The present invention provides for controlling the order in which packets received from across a network may be processed. A receiver station examines the packets and determines a property of the packet. A priority level is associated with the packet prior to processing. The packet is placed into a queue and processed in an order based at least in part on its priority level. The method may be used to expedite or slow the processing of particular packets, such as advancing the processing order for acknowledgment packets. In addition, other aspects of the present invention relating to determining an order for processing packets by a receiver station.
    Type: Grant
    Filed: June 25, 2001
    Date of Patent: January 16, 2007
    Assignee: Intel Corporation
    Inventor: Patrick L. Connor