Abstract: An apparatus for axially aligning a first coupling member and a second coupling member that can be connected so as to form a rotating assembly. The apparatus includes a measurement arrangement configured to be mounted onto the first coupling member and to be rotated therewith. The measurement arrangement includes an emitter arrangement configured to emit first and second signals in the direction of the second coupling member so as to cause at least a portion of said first and second signals to be reflected by the second coupling member. The measurement apparatus further has a capture arrangement configured to capture at least a portion of the first and second reflected signals. The apparatus includes a control arrangement configured to determine an offset in axial alignment between the first and second coupling member based on at least the first and second reflected signals.

Abstract: A system, method, and adapter for creating fault-tolerant communication busses from standard components, are described. Fault-tolerant interface logic is provided for transmitting and receiving system health and system management signals to and from a module that is designed to be connected to a single RS-485 bus. The fault-tolerant interface logic enables the module to selectively communicate via at least two redundant half-duplex, multipoint, differential RS-485 busses. The fault-tolerant interface logic includes a first RS-485 transceiver connected to a first RS-485 bus, a second RS-485 transceiver connected to a second RS-485 bus, selector logic responsive to a control signal for selecting one of the first and the second busses to receive signals from and for transmitting the received signals to the module, and software logic executable on a baseboard management controller (BMC) chip.

Abstract: A method and system for aggregating a plurality of parallel communications links transmitting data between adjacent nodes in a network is provided. The method simplifies network topology by replacing multiple parallel communications links between nodes in the network with a single aggregated link. The method advertises the available bandwidth of each aggregated link to the network, the available bandwidth being the maximum bandwidth available for any one of the parallel links in the aggregate. The method permits each aggregated link to select which of the parallel links in the aggregate is to be used to transfer data from one node to the other. Aggregating links can be automatic and based on one or more predetermined criteria, such as the service class supported by the parallel links.

Abstract: A platform for and method of computer processing to support processor failover are disclosed. A plurality of computer processors are connected to an internal communication network. A virtual local area communication network over the internal network is defined and established. Each computer processor in the virtual local area communication network has a corresponding virtual MAC address and the virtual local area network provides communication among a set of computer processors but excludes the processors from the plurality not in the defined set. A virtual storage space is defined and established with a defined correspondence to the address space of the storage network. In response to a failure by a computer processor, a computer processor from the plurality is allocated to replace the failed processor. The MAC address of the failed processor is assigned to the processor that replaces the failed processor.

Abstract: A platform and method of deploying virtual processing areas networks are described. A plurality of computer processors are connected to an internal communication network. At least one control node is in communication with an external communication network and an external storage network has an external storage address space. The at least one control node is connected to the internal network and thereby is in communication with the plurality of computer processors. Configuration logic defines and establishes a virtual processing area network having a corresponding set of computer processors from the plurality of processors, a virtual local area communication network providing communication among the set of computer processors, and a virtual storage space with a defined correspondence to the address space of the storage network.

Abstract: A platform and method of deploying virtual processing areas networks are described. A plurality of computer processors are connected to an internal communication network. At least one control node is in communication with an external communication network and an external storage network has an external storage address space. The at least one control node is connected to the internal network and thereby is in communication with the plurality of computer processors. Configuration logic defines and establishes a virtual processing area network having a corresponding set of computer processors from the plurality of processors, a virtual local area communication network providing communication among the set of computer processors, and a virtual storage space with a defined correspondence to the address space of the storage network.

Abstract: A platform and method of deploying virtual processing areas networks are described. A plurality of computer processors are connected to an internal communication network. At least one control node is in communication with an external communication network and an external storage network has an external storage address space. The at least one control node is connected to the internal network and thereby is in communication with the plurality of computer processors. Configuration logic defines and establishes a virtual processing area network having a corresponding set of computer processors from the plurality of processors, a virtual local area communication network providing communication among the set of computer processors, and a virtual storage space with a defined correspondence to the address space of the storage network.

Abstract: A high profile rocker arm assembly increases rocker arm strength, minimizes rocker arm weight and enables improved valve lash adjustment. The rocker arm assembly comprises a rocker arm, a cross shaft, and an externally mounted roller tip. The cross shaft incorporates certain offset structure so that when adjustment thereof is made, valve lash adjustment is quickly and easily achieved. This eliminates the need for an adjuster stud and nut on the rocker arm. Several different pillow blocks may function to operatively retain the device.

Abstract: A platform and method of deploying virtual processing areas networks are described. A plurality of computer processors are connected to an internal communication network. At least one control node is in communication with an external communication network and an external storage network has an external storage address space. The at least one control node is connected to the internal network and thereby is in communication with the plurality of computer processors. Configuration logic defines and establishes a virtual processing area network having a corresponding set of computer processors from the plurality of processors, a virtual local area communication network providing communication among the set of computer processors, and a virtual storage space with a defined correspondence to the address space of the storage network.

Abstract: A virtual networking system and method are disclosed. Switched Ethernet local area network semantics are provided over an underlying point to point mesh. Computer processor nodes may directly communicate via virtual interfaces over a switch fabric or they may communicate via an ethernet switch emulation. Address resolution protocol logic helps associate IP addresses with virtual interfaces while allowing computer processors to reply to ARP requests with virtual MAC addresses.

Abstract: The present invention discloses a solar array cell (15) able to be used both thermally and photovoltaically, together with an array (3) formed from a plurality of the cells (15). A solar energy system for a building which incorporates the array (3) is also disclosed. Each cell (15) is formed from an air duct (16) of parallelogram cross-sectional shape which makes for easy sealing between ducts and a reliable water shedding arrangement for the cells of the array. An air/liquid heat exchanger (35) for a solar hot water supply is also disclosed.

Abstract: A platform for and method of computer processing to support processor failover are disclosed. A plurality of computer processors are connected to an internal communication network. A virtual local area communication network over the internal network is defined and established. Each computer processor in the virtual local area communication network has a corresponding virtual MAC address and the virtual local area network provides communication among a set of computer processors but excludes the processors from the plurality not in the defined set. A virtual storage space is defined and established with a defined correspondence to the address space of the storage network. In response to a failure by a computer processor, a computer processor from the plurality is allocated to replace the failed processor. The MAC address of the failed processor is assigned to the processor that replaces the failed processor.

Abstract: A platform for and method of computer processing to support processor failover are disclosed. A plurality of computer processors are connected to an internal communication network. A virtual local area communication network over the internal network is defined and established. Each computer processor in the virtual local area communication network has a corresponding virtual MAC address and the virtual local area network provides communication among a set of computer processors but excludes the processors from the plurality not in the defined set. A virtual storage space is defined and established with a defined correspondence to the address space of the storage network. In response to a failure by a computer processor, a computer processor from the plurality is allocated to replace the failed processor. The MAC address of the failed processor is assigned to the processor that replaces the failed processor.

Abstract: A virtual networking system and method are disclosed. Switched Ethernet local area network semantics are provided over an underlying point to point mesh. Computer processor nodes may directly communicate via virtual interfaces over a switch fabric or they may communicate via an ethernet switch emulation. Address resolution protocol logic helps associate IP addresses with virtual interfaces while allowing computer processors to reply to ARP requests with virtual MAC addresses.

Abstract: A platform and method of deploying virtual processing areas networks are described. A plurality of computer processors are connected to an internal communication network. At least one control node is in communication with an external communication network and an external storage network has an external storage address space. The at least one control node is connected to the internal network and thereby is in communication with the plurality of computer processors. Configuration logic defines and establishes a virtual processing area network having a corresponding set of computer processors from the plurality of processors, a virtual local area communication network providing communication among the set of computer processors, and a virtual storage space with a defined correspondence to the address space of the storage network.

Abstract: A platform for and method of computer processing to support processor failover are disclosed. A plurality of computer processors are connected to an internal communication network. A virtual local area communication network over the internal network is defined and established. Each computer processor in the virtual local area communication network has a corresponding virtual MAC address and the virtual local area network provides communication among a set of computer processors but excludes the processors from the plurality not in the defined set. A virtual storage space is defined and established with a defined correspondence to the address space of the storage network. In response to a failure by a computer processor, a computer processor from the plurality is allocated to replace the failed processor. The MAC address of the failed processor is assigned to the processor that replaces the failed processor.

Abstract: A virtual networking system and method are disclosed. Switched Ethernet local area network semantics are provided over an underlying point to point mesh. Computer processor nodes may directly communicate via virtual interfaces over a switch fabric or they may communicate via an ethernet switch emulation. Address resolution protocol logic helps associate IP addresses with virtual interfaces while allowing computer processors to reply to ARP requests with virtual MAC addresses.

Abstract: This invention is directed to the production of plants, plant tissues and seeds which are resistant to inhibition by an herbicide which normally inhibits the growth and development of those plants, plant tissues and plant seeds. In particular this invention is directed to altered acetohydroxyacid synthase enzymes which are resistant to inhibition by herbicides which normally inhibit the activity of the synthase before such alteration. This invention further relates to genes encoding such enzymes, and to processes for utilizing these novel genes and enzymes. Further products of the invention include plants, plant tissues and seeds which exhibit resistance to such herbicides resulting from expression of genes encoding herbicide resistant acetohydroxyacid synthase enzyme.

Abstract: This invention is directed to the production of plants, plant tissues and seeds which are resistant to inhibition by an herbicide which normally inhibits the growth and development of those plants, plant tissues and plant seeds. In particular this invention is directed to altered acetohydroxyacid synthase enzymes which are resistant to inhibition by herbicides which normally inhibit the activity of the synthase before such alteration. This invention further relates to genes encoding such enzymes, and to processes for utilizing these novel genes and enzymes. Further products of the invention include plants, plant tissues and seeds which exhibit resistance to such herbicides resulting from expression of genes encoding herbicide resistant acetohydroxyacid synthase enzyme.

Abstract: This invention is directed to the production of plants, plant tissues and seeds which are resistant to inhibition by an herbicide which normally inhibits the growth and development of those plants, plant tissues and plant seeds. In particular this invention is directed to altered acetohydroxyacid synthase enzymes which are resistant to inhibition by herbicides which normally inhibit the activity of the synthase before such alteration. This invention further relates to genes encoding such enzymes, and to processes for utilizing these novel genes and enzymes. Further products of the invention include plants, plant tissues and seeds which exhibit resistance to such herbicides resulting from expression of genes encoding herbicide resistant acetohydroxyacid synthase enzyme.