Abstract: A method and system for independently resetting primary and secondary processors 20 and 120 respectively under program control in a multiprocessor, cache memory system. Processors 20 and 120 are reset without causing cache memory controllers 24 and 124 to reset.

Abstract: A computer system provides a 48-bit timer having 120 ns resolution and possessing a rollover period in excess of one year. The preferred embodiment includes two system data buffers (SDBs), each of which includes a full 48-bit timer. The timers are synchronized, and the output of each timer is provided to the host bus in alternating pairs of bits, so that half of the data bits are provided by the first SDB and half of the timer bits are provided by the second SDB. The timer may be read either as a 48-bit timer or a 32-bit timer.

Abstract: The present invention includes two variations of an apparatus which generate a version of the IORC* bus signal that is supplied to the read strobe input of a floppy disk controller that is asserted at the appropriate time during verify cycles between the floppy disk controller and a DMA controller. These designs allow an 82077 floppy disk controller to operate properly in FIFO mode when it is being used with software that does not require generation of this signal. The designs include use of a PAL and certain bus signal inputs to generate a signal which is asserted at the appropriate times during verify transfers. This signal is combined with the regular IORC* bus signal to produce the signal that is provided to the read strobe input of the floppy disk controller.

Abstract: An arrangement of direct memory access (DMA), interrupt and timer functions in a multiprocessor computer system to allow symmetrical processing. Several functions which are considered common to all of the CPUs and those which are conveniently accessed through an expansion bus remain in a central system peripheral chip coupled to the expansion bus. These central functions include the primary portions of the DMA controller and arbitration circuitry to control access of the expansion bus. A distributed peripheral, including a programmable interrupt controller, multiprocessor interrupt logic, nonmaskable interrupt logic, local DMA logic and timer functions, is provided locally for each CPU. A bus is provided between the central and distributed peripherals to allow the central peripheral to broadcast information to the CPUs, and to provide local information from the distributed chip to the central peripheral when the local CPU is programming or accessing functions in the central peripheral.

Abstract: A method of starting up a system clock that has been generated by a phase-locked loop and correcting edge placement errors during coasting periods of the phase locked loop, and circuitry for accomplishing those methods. A low frequency master clock signal is distributed to circuits that generate high frequency local clock signals. These circuits generate the high frequency local clock signals using phase-locked loops in a frequency multiplier configuration. Lock indicator circuitry determines when the phase-locked loop has locked onto the master clock signal and then enables output buffers that then provide the high frequency clock signals to components in the system which need those local clocks. An intermediate frequency signal is fed back to the input of the voltage controlled oscillator in the phase locked loop to correct edge placement errors. A slightly earlier or leading version of the signal is used to correct cycle length variations without inducing duty cycle variations.

Abstract: A method and apparatus for arbitrating between multiple processors that can be incorporated into an arbitration scheme that is designed to include only a single processor. The method includes consolidating the individual bus requests of each processor into a single bus request supplied to the single processor arbitration scheme. When control of the bus is allocated to the single processor, the multiprocessor arbitration arbitrates among the processors who requested the bus. The bus protocol used includes a least recently used method for granting bus access to the multiple processors coupled with a means for giving one processor priority over the others for access to the bus. The protocol also includes protection from interruption for the respective processor in control of the bus for a preset period of time.

Abstract: A method and apparatus which maintains strict ordering of processor cycles to guarantee that a processor write, such as an EOI instruction, is not executed to the interrupt controller prior to the interrupt request from a requesting device being cleared at the interrupt controller, thus maintaining system integrity. Interrupt controller logic is included on each respective CPU board. The processor can access the interrupt controller over a local bus without having to access the host bus or the expansion bus and thus an interrupt controller access could be completed before a previously generated I/O cycle has completed. Therefore, the apparatus which tracks expansion bus cycles and interrupt controller accesses and maintains strict ordering of these cycles to guarantee that an interrupt request is cleared at the interrupt controller prior to execution of write operation to the interrupt controller.

Abstract: A memory mapping and module enabling circuit for allowing logical 128 kbyte memory blocks to be defined for any location in any module connected to a memory system. A RAM is addressed by the system address lines defining 128 kbyte blocks, with the output data providing the row address strobe enable signals for a particular memory module and the address values necessary to place the 128 kbyte block within the module. Various other parameters such as write protect status and memory location are also provided by the RAM. Circuits and techniques for programming and reading the RAM are provided.

Abstract: The present invention includes two variations of an apparatus which generate a version of the IORC* bus signal that is supplied to the read strobe input of a floppy disk controller that is asserted at the appropriate time during verify cycles between the floppy disk controller and a DMA controller. These designs allow an 82077 floppy disk controller to operate properly in FIFO mode when it is being used with software that does not require generation of this signal. The designs include use of a PAL and certain bus signal inputs to generate a signal which is asserted at the appropriate times during verify transfers. This signal is combined with the regular IORC* bus signal to produce the signal that is provided to the read strobe input of the floppy disk controller.

Abstract: A computer system has a processor coupled to a cache controller, uses page mode memory devices and performs page hit detection on the processor local bus. Column address and data values are latched by a memory controller on memory write operations to allow early completion of the cycle so that the next cycle can partially overlap. This allows the use of economical memories and yet have zero wait state page hit operation.

Abstract: Two independently operating microprocessors share common control, data and address buses. A first of the microprocessors is assigned, when it is on the buses, to respond to all maskable interrupts by causing placement of an interrupt vector on the bus at the start of the next bus cycle. When the second microprocessor is on the buses and a maskable interrupt is received, the start of the next bus cycle is inhibited from causing an interrupt vector to be placed on the bus.

Abstract: A computer system which includes a direct memory access (DMA) controller which can provide a 32 bit memory address and yet can also provide 24 bit memory address operation to remain compatible with previous systems. The DMA controller also monitors system operation and if only 24 bit address operations are occurring under the control of an external bus master or the DMA controller, the DMA controller drives the top memory address byte provided to a cache memory controller to help insure cache coherency. Additionally, the DMA controller can provide optimal time transfers for word width transfer between an odd starting memory address and an even starting input/output port.

Abstract: A computer system uses a random access memory to store memory characteristic information, such as noncacheable status. The memory is coupled to the processor address lines to produce an output representative of the memory address block, the output used as appropriate, for example by the noncacheable address input of a cache controller. Latches are used to store programming mode, write or read operation and data values. The reading and writing of the random access memory is performed without disturbing the main memory.

Abstract: A bus arbitration protocol and accompanying bus arbitration logic for multiple-processor computer systems in which each processing module has a local cache. Several bus arbitration policies are enforced on contending devices which effectively introduce delay states into the arbitration behavior exhibited by each device. The bus arbitration protocol employs a distributed method of arbitration control involving an essentially fixed prioritization of arbitrating devices.

Abstract: A computer system which utilizes two different sets of address control and state information signals for transferring information of the same or different widths is disclosed. The use of two sets of signals allows master units to utilize only one set and a system board determines when the second set of signals must be used to complete the transfer and controls the second set of signals as necessary. The system board provides the necessary information routing and latching to properly transfer the information.

Abstract: An enhanced processor lock cycle management system for computer systems including a processor 10 and a cache memory controller 12 which accommodates existing methodologies and provides an enhanced mode wherein processor lock cycles are not passed to the controlled 12 but control of the system bus 14 by controller 12 is maintained by inhibiting hold requests to the controller 12 by other system elements.

Abstract: The present invention is a computer system which can perform master unit controlled memory accesses at a first rate, DMA controlled operations at a second rate and burst operations of both types at a higher third rate. The burst operation is set up by performing a standard access cycle, thus setting up the dynamic random access memory row address, and then performing a series of fast, column address-only accesses to the same page of memory. The fast mode must be exited to a standard rate access whenever a page boundary is crossed, with burst operations recommencing thereafter. Wait states can be inserted in all type operations. Thirty-two bit master units can downshift or step down to 16 bit operation to respond to 16 bit burstable responding units.

Abstract: A fast logic system for decoding addresses for the purpose of designating areas of memory as noncacheable is disclosed. The logic system is based on a programmable array logic having as inputs selected address lines, certain switch settings, and software-selectable diagnostic settings.

Abstract: A personal computer is disclosed having a high speed microprocessor which executes in a variety of selectable speed modes to provide greater compatibility with application programs written for slower speed microprocessors. A logic means is included responsive to a speed select signal which does not change the speed of the microprocessor oscillator (clock) but rather changes the length of a wait state or "STOP" state of the microprocessor. In the STOP state the microprocessor (CPU) does not run bus cycles until the timer times out thereby releasing the CPU STOP. By varying the length of the time delay of the one-shot timer, the microprocessor simulates microprocessor speed changes which have the appearance of earlier generation computers with older microprocessors.

Abstract: A personal computer transfers the contents of the computer's slow 16 bit read only memory (ROM) into the computer's fast 32 bit random access memory (RAM), remaps the RAM space to include the ROM space and disables the ROM. Portions of the RAM are tested before the contents are transferred. After the transfer the computer operates out of the RAM. Additionally, the RAM address space containing the ROM contents can selectively be made write protected so that the data cannot be changed.