Abstract: A computer system which utilizes two different sets of address control and state information signals for transferring data of different widths is disclosed. The use of two sets of signals allows master units to utilize only one set and a system board determines when the second set of signals must be used to complete the transfer and controls the second set of signals as necessary. The system board provides the necessary data routing and latching to properly transfer the data.

Abstract: A computer system including a programmable interrupt controller wherein individual interrupt levels can be programmed to receive edge or level sensed interrupt signals. The controller includes a programmable register for storing the interrupt level designations for each interrupt level and associated interrupt recognition logic.

Abstract: A computer system which flushes the cache controller when a circuit board is being configured or is responding to an input/output write operation. The flush operation can be disabled for each circuit board location. A cache flush operation can also be directly requested.

Abstract: A fast logic system for decoding addresses for the purpose of designating areas of memory as non-cacheable is disclosed. The logic system is based on a programmable array logic having as inputs selected address lines, certain switch settings, and software-selectable diagnostic settings.

Abstract: The present invention is a computer system which can perform master unit controlled memory accesses at a first rate, DMA controlled operations at a second rate and burst operations of both types at a higher third rate. The burst operation is set up by performing a standard access cycle, thus setting up the dynamic random access memory row address, and then performing a series of fast, column address-only accesses to the same page of memory. The fast mode must be exited to a standard rate access whenever a page boundary is crossed, with burst operations recommencing thereafter. Wait states can be inserted in all type operations. Timing diagrams and controller state machines are disclosed.

Abstract: An apparatus for determining maximum usable memory size is disclosed. Permanent connections on a base memory unit and additional memory modules provide signals indicative of the amount of memory installed at each location. The signals are read by the processor and used in conjunction with a lookup table or size counting method to determine maximum usable memory size and the existence of installation or operation errors. The maximum size is written to a latch which provides the value to logic which enables the appropriate memory locations when addressed by the processor.

Abstract: An extended addressing system for allowing use of existing circuit boards but obtaining more address space is disclosed. If given bits in the address value indicate that a former system board address is being presented previously unutilized higher order bits are used as a slot identifier that slot's AEN signal is made low, while all the remaining AEN signals to each slot are made high to disable operation. All the AEN lines remain low as an existing circuit board address is presented or a memory operation is occurring. All the AEN lines go high during a DMA operation.

Abstract: A personal computer is disclosed having a high speed microprocessor which executes in either a FAST mode or a SLOW mode application programs written for a slow speed microprocessor. The slow speed microprocessor contains a pre-fetch queue that is smaller than the pre-fetch queue of the high speed microprocessor. A logic means is included, responsive to a mode select signal for controlling the wait state of said high speed microprocessor when in the SLOW speed mode so that every other word accessed to said RAM memory requires two consecutive word accesses to the same memory address to obtain the contents of the addressed location thereby enabling said high speed microprocessor to execute applications programs in the SLOW mode, on the average, at substantially the same speed as the program normally runs on the slow speed microprocessor.

Abstract: A personal computer is disclosed having a microprocessor RESET/HOLD arbitration circuit and logic. The RESET/HOLD arbitration circuit requires a RESET signal to wait until any pending microprocessor "HOLD" is serviced or in the alternative and in the event the "RESET" signal is being processed causes the microprocessor "HOLD" signal to wait. The priority arbitration circuit and logic is essential to the proper operation of the 80386 microprocessor particularly in shifting from the "protected" mode of the microprocessor to the "real" mode of the microprocessor, since many third party application programs require the use of the microprocessor "protected" mode and require that the microprocessor be "reset" before returning to the "real" mode. The microprocessor "reset" must be accomplished by resetting the microprocessor without resetting the entire machine and without losing a HOLD request during the RESET.

Abstract: A personal computer is disclosed having a high speed microprocessor which executes in either a FAST mode or a SLOW mode application programs written for a slow speed microprocessor. The slow speed microprocessor contains a pre-fetch queue that is smaller than the pre-fetch queue of the high speed microprocessor. A logic means is included, responsive to a mode select signal for controlling the wait state of said high speed microprocessor when in the SLOW speed mode so that every other word accessed to said RAM memory requires two consecutive word accesses to the same memory address to obtain the contents of the addressed location thereby enabling said high speed microprocessor to execute application programs in the SLOW mode, on the average, at substantially the same speed as the program normally runs on the slow speed microprocessor.

Abstract: The present invention relates to a video display controller system which permits a variety of differing video attributes for each displayed character. A character code is stored in a character memory and an attribute code is stored in an attribute memory at corresponding memory locations for each display position. In accordance with the present invention the transfer of data to and from the attribute memory is through an attribute latch. Each time a character is written into the character memory the attribute stored in the attribute latch is stored in the corresponding location in the attribute memory. Similarly, the attribute stored in the corresponding location of the attribute memory is stored in the attribute latch upon reading a character from the character memory. The attribute latch can be independently read out or written into. This technique is advantageous for specifying a display screen in which many characters have the same video attribute and for executing block moves within the display screen.

Abstract: An electronic thermal printer has a thermal printhead to which is applied a train of pulses which is pulse width modulated. A power switch connects and disconnects the printhead from a DC power source. The pulse train is integrated, scaled and applied as an input to a comparator circuit. The thermal printhead has a temperature sensing diode whose output is applied, as a reference voltage, to the other input of the comparator. During a print cycle, the output of the temperature sensing diode is cut off and the reference voltage is capacitively stored and held as the reference voltage. The output of the comparator circuit clears a latch circuit whose input is provided by a system clock and whose output is connected to control the power switch. The comparator provides an output when the integrated voltage reaches the reference voltage, clearing the latch. Since the latch is supplied with signals from the system clock, a constant frequency is maintained.