Abstract: Multiplexing data from bitstreams is described. Data status is determined for data of each of the bitstreams. Stream numbers are assigned respectively to the bitstreams, and the data of each of the bitstreams is controllably stored in respective memory. A memory buffer of the memory buffers is controllably selected. The data obtained from the memory buffer selected is parsed to provide an output. The controllably selecting and the parsing are repeated to obtain and parse the data stored in at least one other memory buffer of the memory buffers to provide the output. The output is multiplexed data from the bitstreams respectively associated with the memory buffer and the at least one other memory buffer.

Abstract: Method and apparatus for communication of data is described. More particularly, generation of an interface for coupling to an auxiliary processor unit for communication of data in an integrated circuit is described. Programmable logic is programmed to provide a hardware interface for communicating the data between memory and a user-defined circuit. The data is communicated at least in part via an auxiliary processor unit coupled to the hardware interface. The programming includes configuring the programmable logic to use the auxiliary processor unit to respond to coded instructions executed by a central processing unit through the provided hardware interface.

Abstract: Method and apparatus for processing a dataflow description of a digital processing system is described. In one example, a model of the dataflow description is simulated. Computational steps performed during the simulation and actual dependencies among the computational steps resulting from the simulation are identified. Causation trace data is generated in response to the step of recording. The causation trace data may then be analyzed using one or more analyses to produce quantitative data that characterizes the dataflow description.

Abstract: Method and apparatus for communication between hardware blocks configured in a programmable logic device (PLD) and a computation device external to the PLD is described. A bus controller is provided for receiving words from the computation device. Each of the words includes an address component and a data component. A first-in-first-out buffer (FIFO) is configured for communication with the bus controller to store the words. A processing engine is provided having a memory space associated with the hardware blocks and being configured to receive a word at a top of the FIFO. An address decoder is provided for decoding the address component of the word at the top of the FIFO to obtain an address of a memory location in the memory space. A strobe generator is provided for coupling a strobe signal to the processing engine. The strobe signal is configured to store the word in the memory location.

Abstract: Method and apparatus for implementing first-in-first-out (FIFO) memories using time-multiplexed memory in an integrated circuit are described. A block random access memory (BRAM) circuit embedded in the integrated circuit is provided. The BRAM includes at least one port responsive to a respective at least one BRAM clock signal. FIFO logic is configured to implement a plurality of FIFOs in the BRAM having a plurality of interfaces. Multiplexer logic is configured to selectively couple the plurality of output interfaces of the FIFO logic to the at least one port of the BRAM circuit responsive to at least one FIFO clock signal. Each of the at least one BRAM clock signal has at least twice the frequency of a respective one of the at least one FIFO clock signal.

Abstract: Method and apparatus for communication between hardware blocks and a processor in a programmable logic device is described. A shared memory is provided along with a memory controller for controlling access to the shared memory. An interface is configured to receive auxiliary instructions from the processor, select the hardware blocks for the requested tasks in response to the auxiliary instructions, notify the hardware blocks of those tasks, and arbitrate access to the memory controller among the hardware blocks.

Abstract: Various approaches for embedding identifier information in a configuration bitstream for a programmable logic device (PLD) are disclosed. In various embodiments, the bits in the configuration bitstream that are unused in implementing a the design are identified. The identifier information is encrypted, and a subset of the unused bits are selected using a pseudo-random function. The encrypted identifier information is placed in the selected subset of unused bits. Decryption is accomplished by reversing the encryption approach.

Abstract: An extended bitstream, and generation thereof, for dynamically configuring a decoder. Content data is obtained to be encoded. Build settings are obtained for configuring the decoder. The content data is encoded with an encoder to provide encoded data. A configuration bitstream is generated for configuring programmable logic responsive to the build settings. The configuration bitstream is combined with the encoded data to provide the extended bitstream. The extended bitstream is self-contained to allow for configuring of the programmable logic to dynamically instantiate the decoder to decode the encoded data.

Abstract: Method and apparatus for designing a system for implementation in a programmable logic device (PLD) is described. In one example, a program language description of the system is captured. The program language description includes control code for configuring actor elements with functions to perform tasks in response to input data. A hardware implementation is generated for the PLD from the program language description by mapping the control code to decision logic, the functions to partial configuration streams, and the actor elements to reconfigurable slots.

Abstract: An aspect of the invention relates to communication between a first processing element and a second processing element. A first-in-first-out circuit (FIFO) includes a data input port, a data output port, an object-sent port, an object-end port, a memory, and control logic. The data input port is coupled to the first processing element. The data output port is coupled to the second processing element. The object-sent port is configured to receive an object-sent signal from the first processing element. The object-end port is configured to send an object-end signal to the second processing element. The memory is configured to store objects, each of the objects include a plurality of data words. The control logic is configured to control reading and writing to the memory, processing the object sent signal, and generating the object end signal.

Abstract: Method and apparatus for encoding image data is described. In an example, a memory stores bit-planes associated with the image data. Each of the bit-planes is partitioned into data units. A bit modeler communicates with the memory and produces modeled data in response to each of the data units for each of the bit-planes. An arithmetic coder communicates with the bit modeler and produces a coded data in response to each of the modeled data produced by the bit-modeler. In another example, the bit-modeler processes at least two of the bit-planes in parallel.

Abstract: Method and apparatus for processing data stored in a memory shared among a plurality of processors is described. In an example, a semaphore is provided that is associated with a first portion of the memory. Tasks are stored in the first portion of the memory, the tasks being respectively related to data segments stored in a second portion of the memory. A state of the semaphore is determined. Access among the plurality of processors to the first portion of the memory is controlled in response to the state of the semaphore. A task is executed to process a data segment of the data segments in response to a processor of the plurality of processors gaining access to the first portion of the memory.

Abstract: The invention is a crane system for a building for the assembly of a gas bag for a lighter-than-air vehicle, the building having a floor and a roof thereover with a longitudinal, vertical and lateral axis. In detail, the crane assembly includes a plurality of crane carriage rail assemblies in the form of arches aligned with the lateral axis of and mounted within the building. The carriage rail assemblies are in a spaced relationship along the longitudinal axis. A plurality of crane carriages are movably mounted on each of the crane rail assemblies with each carriage including a winch mounted thereon having an extendible and retractable cable. A control system is provided for moving the crane carriages by rows aligned with the longitudinal axis of the building along the crane carriage rail assemblies to specific locations along the lateral axis and for adjusting the length of the cables of the winches in each of the rows as a function of the distance of each of the rows along the lateral axis of the building.