Patents by Inventor Paul W. Coteus

Paul W. Coteus has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Implementing inverted master-slave 3D semiconductor stack
    Patent number: 10068886
    Abstract: A method and apparatus are provided for implementing an enhanced three dimensional (3D) semiconductor stack. A chip carrier has an aperture of a first length and first width. A first chip has at least one of a second length greater than the first length or a second width greater than the first width; a second chip attached to the first chip, the second chip having at least one of a third length less than the first length or a third width less than the first width; the first chip attached to the chip carrier by connections in an overlap region defined by at least one of the first and second lengths or the first and second widths; the second chip extending into the aperture; and a heat spreader attached to the chip carrier and in thermal contact with the first chip for dissipating heat from both the first chip and second chip.
    Type: Grant
    Filed: April 29, 2015
    Date of Patent: September 4, 2018
    Assignee: International Business Machines Corporation
    Inventors: Paul W. Coteus, Shawn A. Hall, Todd E. Takken
  • Collective network for computer structures
    Patent number: 10069599
    Abstract: A system and method for enabling high-speed, low-latency global collective communications among interconnected processing nodes. The global collective network optimally enables collective reduction operations to be performed during parallel algorithm operations executing in a computer structure having a plurality of the interconnected processing nodes. Router devices are included that interconnect the nodes of the network via links to facilitate performance of low-latency global processing operations at nodes of the virtual network and class structures. The global collective network may be configured to provide global barrier and interrupt functionality in asynchronous or synchronized manner. When implemented in a massively-parallel supercomputing structure, the global collective network is physically and logically partitionable according to needs of a processing algorithm.
    Type: Grant
    Filed: December 17, 2015
    Date of Patent: September 4, 2018
    Assignee: International Business Machines Corporation
    Inventors: Matthias A. Blumrich, Paul W. Coteus, Dong Chen, Alan Gara, Mark E. Giampapa, Philip Heidelberger, Dirk Hoenicke, Todd E. Takken, Burkhard D. Steinmacher-Burow, Pavlos M. Vranas
  • LOW RESISTANCE, LOW-INDUCTANCE POWER CONNECTORS
    Publication number: 20180138609
    Abstract: An electrical connector includes an anode for conducting an electrical supply current from a source to a destination, a cathode for conducting an electrical return current from the destination to the source, and an insulator that prevents electrical conduction between the anode and the cathode. The first and second shapes are such as to provide a conformity of one to the other, with the insulator placed therebetween and having a predetermined relatively thin thickness. A predetermined low-resistance path for the supply current is provided respectively by the anode and the cathode, and a proximity of the anode to the cathode along these paths provides a predetermined low self-inductance of the connector. The anode and the cathode each comprises a plurality of sections that are disposed at one or more predetermined angles to form a rigid assembly that accommodates a geometry between the source and the destination.
    Type: Application
    Filed: December 28, 2017
    Publication date: May 17, 2018
    Inventors: Paul W. COTEUS, Andrew FERENCZ, Shawn Anthony HALL, Todd Edward TAKKEN
  • Multi-petascale highly efficient parallel supercomputer
    Patent number: 9971713
    Abstract: A Multi-Petascale Highly Efficient Parallel Supercomputer of 100 petaflop-scale includes node architectures based upon System-On-a-Chip technology, where each processing node comprises a single Application Specific Integrated Circuit (ASIC). The ASIC nodes are interconnected by a five dimensional torus network that optimally maximize the throughput of packet communications between nodes and minimize latency. The network implements collective network and a global asynchronous network that provides global barrier and notification functions. Integrated in the node design include a list-based prefetcher. The memory system implements transaction memory, thread level speculation, and multiversioning cache that improves soft error rate at the same time and supports DMA functionality allowing for parallel processing message-passing.
    Type: Grant
    Filed: April 30, 2015
    Date of Patent: May 15, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Sameh Asaad, Ralph E. Bellofatto, Michael A. Blocksome, Matthias A. Blumrich, Peter Boyle, Jose R. Brunheroto, Dong Chen, Chen-Yong Cher, George L. Chiu, Norman Christ, Paul W. Coteus, Kristan D. Davis, Gabor J. Dozsa, Alexandre E. Eichenberger, Noel A. Eisley, Matthew R. Ellavsky, Kahn C. Evans, Bruce M. Fleischer, Thomas W. Fox, Alan Gara, Mark E. Giampapa, Thomas M. Gooding, Michael K. Gschwind, John A. Gunnels, Shawn A. Hall, Rudolf A. Haring, Philip Heidelberger, Todd A. Inglett, Brant L. Knudson, Gerard V. Kopcsay, Sameer Kumar, Amith R. Mamidala, James A. Marcella, Mark G. Megerian, Douglas R. Miller, Samuel J. Miller, Adam J. Muff, Michael B. Mundy, John K. O'Brien, Kathryn M. O'Brien, Martin Ohmacht, Jeffrey J. Parker, Ruth J. Poole, Joseph D. Ratterman, Valentina Salapura, David L. Satterfield, Robert M. Senger, Burkhard Steinmacher-Burow, William M. Stockdell, Craig B. Stunkel, Krishnan Sugavanam, Yutaka Sugawara, Todd E. Takken, Barry M. Trager, James L. Van Oosten, Charles D. Wait, Robert E. Walkup, Alfred T. Watson, Robert W. Wisniewski, Peng Wu
  • Open-loop quadrature clock corrector and generator
    Patent number: 9912324
    Abstract: Embodiments described herein include a quadrature phase corrector (QPC) which includes multiple differential amplifies for correcting the phase of one or more clock signals. In one embodiment, the differential amplifiers are arranged in an input stage, cross-coupled stage, and ring stage. The input stage receives and buffers the input clock signal (or signals). The cross-coupled stage includes one or more latches that force one clock signal high and another low which causes the QPC to oscillate. The ring stage outputs four clock signals with adjusted phases relative to the input clock signals. In one example, the ring stage outputs a quadrature clock signal that includes four clock signals phase shifted by 90 degrees.
    Type: Grant
    Filed: September 1, 2015
    Date of Patent: March 6, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Paul W. Coteus, Daniel M. Dreps, Kyu-hyoun Kim, Glen A. Wiedemeier
  • Error feedback and logging with memory on-chip error checking and correcting (ECC)
    Patent number: 9880896
    Abstract: Error checking and correcting (ECC) may be performed in an on-chip memory where an error is corrected by a controller and not the on-chip memory. The controller may be flagged to show that an error has occurred and where it has occurred in the memory. The controller may access ECC bits associated with the error and may fix incorrect data. The error checking may be done in parallel with read operations of the memory so as to lower latency.
    Type: Grant
    Filed: June 30, 2014
    Date of Patent: January 30, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Paul W. Coteus, Hillery C. Hunter, Charles A. Kilmer, Kyu-hyoun Kim, Luis A. Lastras-Montano, Warren E. Maule, Vipinchandra Patel
  • Low resistance, low-inductance power connectors
    Patent number: 9871310
    Abstract: An electrical connector includes an anode assembly for conducting an electrical supply current from a source to a destination, the anode assembly includes an anode formed into a first shape from sheet metal or other sheet-like conducting material. A cathode assembly conducts an electrical return current from the destination to the source, the cathode assembly includes a cathode formed into a second shape from sheet metal or other sheet-like conducting material. An insulator prevents electrical conduction between the anode and the cathode. The first and second shapes are such as to provide a conformity of one to the other, with the insulator therebetween having a predetermined relatively thin thickness.
    Type: Grant
    Filed: December 9, 2015
    Date of Patent: January 16, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Paul W. Coteus, Andrew Ferencz, Shawn Anthony Hall, Todd Edward Takken
  • Power converter using near-load output capacitance, direct inductor contact, and/or remote current sense
    Patent number: 9831783
    Abstract: An apparatus includes a first circuit board including first components including a load, and a second circuit board including second components including switching power devices and an output inductor. Ground and output voltage contacts between the circuit boards are made through soldered or connectorized interfaces. Certain components on the first circuit board and certain components, including the output inductor, on the second circuit board act as a DC-DC voltage converter for the load. An output capacitance for the conversion is on the first circuit board with no board-to-board interface between the output capacitance and the load. The inductance of the board-to-board interface functions as part of the output inductor's inductance and not as a parasitic inductance. Sense components for sensing current through the output inductor are located on the first circuit board. Parasitic inductance of the board-to-board interface has less effect on a sense signal provided to a controller.
    Type: Grant
    Filed: December 30, 2015
    Date of Patent: November 28, 2017
    Assignee: International Business Machines Corporation
    Inventors: Paul W Coteus, Andrew Ferencz, Shawn A Hall, Todd E Takken, Shurong Tian, Xin Zhang
  • Thermal-and spatial-aware task scheduling
    Patent number: 9817697
    Abstract: A method, apparatus, and computer program product are provided for thermal- and spatial-aware task scheduling. The method may include monitoring a temperature for each core of a central processing unit having a plurality of cores; determining, from the monitoring, a set of hotspot cores from the plurality of cores determining temperature information and distance information for each hotspot core in the set of hotspot cores relative to each of the other cores on the central processing unit; calculating a placement metric for each core of the central processing unit based at least on the determined distance information and the determined temperature information; and scheduling a task by allocating the task to one or more cores of the central processing unit according to the placement metric.
    Type: Grant
    Filed: March 25, 2016
    Date of Patent: November 14, 2017
    Assignee: International Business Machines Corporation
    Inventors: Paul W. Coteus, Eun Kyung Lee, Yoonho Park
  • Thermal-And Spatial-Aware Task Scheduling
    Publication number: 20170277564
    Abstract: A method, apparatus, and computer program product are provided for thermal- and spatial-aware task scheduling. The method may include monitoring a temperature for each core of a central processing unit having a plurality of cores; determining, from the monitoring, a set of hotspot cores from the plurality of cores determining temperature information and distance information for each hotspot core in the set of hotspot cores relative to each of the other cores on the central processing unit; calculating a placement metric for each core of the central processing unit based at least on the determined distance information and the determined temperature information; and scheduling a task by allocating the task to one or more cores of the central processing unit according to the placement metric.
    Type: Application
    Filed: March 25, 2016
    Publication date: September 28, 2017
    Inventors: Paul W. Coteus, Eun Kyung Lee, Yoonho Park
  • POWER CONVERTER USING NEAR-LOAD OUTPUT CAPACITANCE, DIRECT INDUCTOR CONTACT, AND/OR REMOTE CURRENT SENSE
    Publication number: 20170194871
    Abstract: An apparatus includes a first circuit board including first components including a load, and a second circuit board including second components including switching power devices and an output inductor. Ground and output voltage contacts between the circuit boards are made through soldered or connectorized interfaces. Certain components on the first circuit board and certain components, including the output inductor, on the second circuit board act as a DC-DC voltage converter for the load. An output capacitance for the conversion is on the first circuit board with no board-to-board interface between the output capacitance and the load. The inductance of the board-to-board interface functions as part of the output inductor's inductance and not as a parasitic inductance. Sense components for sensing current through the output inductor are located on the first circuit board. Parasitic inductance of the board-to-board interface has less effect on a sense signal provided to a controller.
    Type: Application
    Filed: December 30, 2015
    Publication date: July 6, 2017
    Inventors: Paul W. Coteus, Andrew Ferencz, Shawn A. Hall, Todd E. Takken, Shurong Tian, Xin Zhang
  • LOW RESISTANCE, LOW-INDUCTANCE POWER CONNECTORS
    Publication number: 20170170581
    Abstract: An electrical connector includes an anode assembly for conducting an electrical supply current from a source to a destination, the anode assembly includes an anode formed into a first shape from sheet metal or other sheet-like conducting material. A cathode assembly conducts an electrical return current from the destination to the source, the cathode assembly includes a cathode formed into a second shape from sheet metal or other sheet-like conducting material. An insulator prevents electrical conduction between the anode and the cathode. The first and second shapes are such as to provide a conformity of one to the other, with the insulator therebetween having a predetermined relatively thin thickness.
    Type: Application
    Filed: December 9, 2015
    Publication date: June 15, 2017
    Inventors: Paul W. COTEUS, Andrew FERENCZ, Shawn Anthony HALL, Todd Edward TAKKEN
  • HIGH-DENSITY, FAIL-IN-PLACE SWITCHES FOR COMPUTER AND DATA NETWORKS
    Publication number: 20170155598
    Abstract: A structure for a network switch. The network switch may include a plurality of spine chips arranged on a plurality of spine cards, where one or more spine chips are located on each spine card; and a plurality of leaf chips arranged on a plurality of leaf cards, wherein one or more leaf chips are located on each leaf card, where each spine card is connected to every leaf chip and the plurality of spine chips are surrounded on at least two sides by leaf cards.
    Type: Application
    Filed: February 13, 2017
    Publication date: June 1, 2017
    Inventors: Paul W. Coteus, Fuad E. Doany, Shawn A. Hall, Mark D. Schultz, Todd E. Takken, Shurong Tian
  • DISTRIBUTED SERIALIZED DATA BUFFER AND A MEMORY MODULE FOR A CASCADABLE AND EXTENDED MEMORY SUBSYSTEM
    Publication number: 20170115930
    Abstract: Embodiments disclosed herein generally relate to techniques for routing data through one or more cascaded memory modules. Each memory module can include a plurality of data buffers. Each data buffer includes a plurality of ports for routing data to and/or from other memory modules. In one embodiment, the data buffer is configured to route write data to DRAM devices on a first memory module or route write data to a data buffer of at least one downstream memory module. The data buffer is also configured to receive read data from a DRAM device of the first memory module or receive read data from a downstream memory module.
    Type: Application
    Filed: October 22, 2015
    Publication date: April 27, 2017
    Inventors: Paul W. COTEUS, Daniel M. DREPS, Charles A. KILMER, Kyu-hyoun KIM, Warren E. MAULE, Todd E. TAKKEN
  • High-density, fail-in-place switches for computer and data networks
    Patent number: 9634959
    Abstract: A structure for a network switch. The network switch may include a plurality of spine chips arranged on a plurality of spine cards, where one or more spine chips are located on each spine card; and a plurality of leaf chips arranged on a plurality of leaf cards, wherein one or more leaf chips are located on each leaf card, where each spine card is connected to every leaf chip and the plurality of spine chips are surrounded on at least two sides by leaf cards.
    Type: Grant
    Filed: November 20, 2014
    Date of Patent: April 25, 2017
    Assignee: International Business Machines Corporation
    Inventors: Paul W. Coteus, Fuad E. Doany, Shawn A. Hall, Mark D. Schultz, Todd E. Takken, Shurong Tian
  • POWER MANAGEMENT OF NETWORK LINKS
    Publication number: 20170086151
    Abstract: A first method includes determining a total length of pending packets for a network link, determining a currently preferred power mode for the network link based on the total length of pending packets for the network link, and changing a current power mode for the network link to the currently preferred power mode. A corresponding apparatus is also disclosed herein. A second method includes determining a utilization for a network link, determining a currently preferred power mode for the network link based on the utilization for the network link, and changing a current power mode for the network link to the currently preferred power mode. A corresponding apparatus is also disclosed herein.
    Type: Application
    Filed: September 23, 2015
    Publication date: March 23, 2017
    Inventors: Dong Chen, Paul W. Coteus, Noel A. Eisley, Philip Heidelberger, Robert M. Senger, Burkhard Steinmacher-Burow, Yutaka Sugawara
  • OPEN-LOOP QUADRATURE CLOCK CORRECTOR AND GENERATOR
    Publication number: 20170063353
    Abstract: Embodiments described herein include a quadrature phase corrector (QPC) which includes multiple differential amplifies for correcting the phase of one or more clock signals. In one embodiment, the differential amplifiers are arranged in an input stage, cross-coupled stage, and ring stage. The input stage receives and buffers the input clock signal (or signals). The cross-coupled stage includes one or more latches that force one clock signal high and another low which causes the QPC to oscillate. The ring stage outputs four clock signals with adjusted phases relative to the input clock signals. In one example, the ring stage outputs a quadrature clock signal that includes four clock signals phase shifted by 90 degrees.
    Type: Application
    Filed: September 1, 2015
    Publication date: March 2, 2017
    Inventors: Paul W. COTEUS, Daniel M. DREPS, Kyu-hyoun KIM, Glen A. WIEDEMEIER
  • EMBEDDING GLOBAL BARRIER AND COLLECTIVE IN A TORUS NETWORK
    Publication number: 20160316001
    Abstract: Embodiments of the invention provide a method, system and computer program product for embedding a global barrier and global interrupt network in a parallel computer system organized as a torus network. The computer system includes a multitude of nodes. In one embodiment, the method comprises taking inputs from a set of receivers of the nodes, dividing the inputs from the receivers into a plurality of classes, combining the inputs of each of the classes to obtain a result, and sending said result to a set of senders of the nodes. Embodiments of the invention provide a method, system and computer program product for embedding a collective network in a parallel computer system organized as a torus network. In one embodiment, the method comprises adding to a torus network a central collective logic to route messages among at least a group of nodes in a tree structure.
    Type: Application
    Filed: May 20, 2016
    Publication date: October 27, 2016
    Inventors: Dong Chen, Paul W. Coteus, Noel A. Eisley, Alan Gara, Philip Heidelberger, Robert M. Senger, Valentina Salapura, Burkhard Steinmacher-Burow, Yutaka Sugawara, Todd E. Takken
  • FLEXIBLE COLD PLATE WITH ENHANCED FLEXIBILITY
    Publication number: 20160290728
    Abstract: An apparatus for cooling an electronic component has a planar top member of a thermal energy conductive material and a parallel planar bottom member of the material, the planar bottom member including a surface having regions configured for heat exchange contact with the electronic component. The joined planar top and bottom members have a sidewall structure of reduced height (and generally the height of the cold plate) between active areas in order to improve flexibility. The stiffness of the sidewalls is reduced by very advantageously reduce the height of the sidewalls. In one embodiment, the sidewalls are shorter in height corresponding to regions only between active areas. Alternatively, the sidewalls are of reduced height everywhere by insetting the active areas within the top and/or bottom sheets.
    Type: Application
    Filed: August 4, 2015
    Publication date: October 6, 2016
    Inventors: Paul W. Coteus, Shawn A. Hall, Mark D. Schultz, Todd E. Takken, Shurong Tian
  • BURST RESISTANT THIN WALL HEAT SINK
    Publication number: 20160290727
    Abstract: An apparatus for cooling an electronic component has a planar top member of a thermal energy conductive material and a parallel planar bottom member of the material, the planar bottom member including a surface having regions configured for heat exchange contact with the electronic component. The planar top member has a plurality of stamped indent formations at a plurality of locations, each indent formation providing a contact surface such that the planar top member is affixed to the bottom member by braze or solder at each contact surface. Alternatively, the planar bottom member also has a plurality of stamped indent formations in alignment with indent formations of the top member. The planar top member is affixed to the bottom member by brazing or soldering each respective contact surface of an indent formation of the planar top member to an opposing contact surface of a corresponding indent formation of the parallel planar bottom member.
    Type: Application
    Filed: August 4, 2015
    Publication date: October 6, 2016
    Inventors: Paul W. Coteus, Shawn A. Hall, Mark D. Schultz, Todd E. Takken, Shurong Tian