Patents by Inventor Paul W. Coteus

Paul W. Coteus has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • System-wide power management control via clock distribution network
    Patent number: 9037892
    Abstract: An apparatus, method and computer program product for automatically controlling power dissipation of a parallel computing system that includes a plurality of processors. A computing device issues a command to the parallel computing system. A clock pulse-width modulator encodes the command in a system clock signal to be distributed to the plurality of processors. The plurality of processors in the parallel computing system receive the system clock signal including the encoded command, and adjusts power dissipation according to the encoded command.
    Type: Grant
    Filed: April 13, 2011
    Date of Patent: May 19, 2015
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Paul W. Coteus, Alan Gara, Thomas M. Gooding, Rudolf A. Haring, Gerard V. Kopcsay, Thomas A. Liebsch, Don D. Reed
  • Packaging structure
    Patent number: 8927336
    Abstract: A method of assembling a packaging structure is provided and includes directly electrically interconnecting respective active surfaces of first and second chips in a face-to-face arrangement, electrically interconnecting at least one of the respective sidewalls of the first and second chips to a common chip and orienting the respective active surfaces of the first and second chips transversely with respect to the common chip.
    Type: Grant
    Filed: August 15, 2013
    Date of Patent: January 6, 2015
    Assignee: International Business Machines Corporation
    Inventors: Evan G. Colgan, Paul W. Coteus, Robert L. Wisnieff
  • Packaging structure
    Patent number: 8916959
    Abstract: A packaging structure is provided. The packaging structure includes first and second chips, at least one surface of each of the first and second chips being an active surface and a common chip to which at least one of the first and second chips is electrically interconnected. The respective active surfaces of the first and second chips are directly electrically interconnected to one another in a face-to-face arrangement and are oriented transversely with respect to the common chip.
    Type: Grant
    Filed: December 20, 2012
    Date of Patent: December 23, 2014
    Assignee: International Business Machines Corporation
    Inventors: Evan G. Colgan, Paul W. Coteus, Robert L. Wisnieff
  • Implementing timing alignment and synchronized memory activities of multiple memory devices accessed in parallel
    Patent number: 8909878
    Abstract: A method and circuit for implementing synchronized memory activities of multiple memory devices being accessed in parallel, and a design structure on which the subject circuit resides are provided. Each memory circuit generates an internal status signal for predefined internal memory activities and provides an output signal coupled to the multiple memory devices. Each memory circuit monitors the generated internal status signal and the output signal of at least one of the multiple memory devices, and responsive to the monitored signals generates a control signal for adjusting operation of its memory activities to synchronize memory activities of the memory devices.
    Type: Grant
    Filed: June 12, 2012
    Date of Patent: December 9, 2014
    Assignee: International Business Machines Corporation
    Inventors: Paul W. Coteus, Kyu-hyoun Kim
  • Method of forming metallized elastomeric electrical contacts
    Patent number: 8832936
    Abstract: Techniques for forming enhanced electrical connections are provided. In one aspect, a method of forming an electrical connecting device includes the steps of: depositing an elastomeric material on an electrically insulating carrier; and metallizing the elastomeric material so as to form an electrically conductive layer running continuously through a plane of the carrier and along a surface of the elastomeric material.
    Type: Grant
    Filed: July 31, 2009
    Date of Patent: September 16, 2014
    Assignee: International Business Machines Corporation
    Inventors: Gareth Geoffrey Hougham, Ali Afzali, Steven Allen Cordes, Paul W. Coteus, Matthew J. Farinelli, Sherif A. Goma, Alphonso P. Lanzetta, Daniel Peter Morris, Joanna Rosner, Nisha Yohannan
  • EMBEDDING GLOBAL BARRIER AND COLLECTIVE IN A TORUS NETWORK
    Publication number: 20140237045
    Abstract: Embodiments of the invention provide a method, system and computer program product for embedding a global barrier and global interrupt network in a parallel computer system organized as a torus network. The computer system includes a multitude of nodes. In one embodiment, the method comprises taking inputs from a set of receivers of the nodes, dividing the inputs from the receivers into a plurality of classes, combining the inputs of each of the classes to obtain a result, and sending said result to a set of senders of the nodes. Embodiments of the invention provide a method, system and computer program product for embedding a collective network in a parallel computer system organized as a torus network. In one embodiment, the method comprises adding to a torus network a central collective logic to route messages among at least a group of nodes in a tree structure.
    Type: Application
    Filed: August 26, 2013
    Publication date: August 21, 2014
    Applicant: International Business Machines Coroporation
    Inventors: Dong Chen, Paul W. Coteus, Noel A. Eisley, Alan Gara, Philip Heidelberger, Robert M. Senger, Valentina Salapura, Burkhard Steinmacher-Burow, Yutaka Sugawara, Todd E. Takken
  • Non-volatile memory for checkpoint storage
    Patent number: 8788879
    Abstract: A system, method and computer program product for supporting system initiated checkpoints in high performance parallel computing systems and storing of checkpoint data to a non-volatile memory storage device. The system and method generates selective control signals to perform checkpointing of system related data in presence of messaging activity associated with a user application running at the node. The checkpointing is initiated by the system such that checkpoint data of a plurality of network nodes may be obtained even in the presence of user applications running on highly parallel computers that include ongoing user messaging activity. In one embodiment, the non-volatile memory is a pluggable flash memory card.
    Type: Grant
    Filed: January 10, 2011
    Date of Patent: July 22, 2014
    Assignee: International Business Machines Corporation
    Inventors: Matthias A. Blumrich, Dong Chen, Thomas M. Cipolla, Paul W. Coteus, Alan Gara, Philip Heidelberger, Mark J. Jeanson, Gerard V. Kopcsay, Martin Ohmacht, Todd E. Takken
  • PACKAGING STRUCTURE
    Publication number: 20140175635
    Abstract: A packaging structure is provided. The packaging structure includes first and second chips, at least one surface of each of the first and second chips being an active surface and a common chip to which at least one of the first and second chips is electrically interconnected. The respective active surfaces of the first and second chips are directly electrically interconnected to one another in a face-to-face arrangement and are oriented transversely with respect to the common chip.
    Type: Application
    Filed: December 20, 2012
    Publication date: June 26, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Evan G. Colgan, Paul W. Coteus, Robert L. Wisnieff
  • PACKAGING STRUCTURE
    Publication number: 20140179066
    Abstract: A method of assembling a packaging structure is provided and includes directly electrically interconnecting respective active surfaces of first and second chips in a face-to-face arrangement, electrically interconnecting at least one of the respective sidewalls of the first and second chips to a common chip and orienting the respective active surfaces of the first and second chips transversely with respect to the common chip.
    Type: Application
    Filed: August 15, 2013
    Publication date: June 26, 2014
    Applicant: International Business Machines Corporation
    Inventors: Evan G. Colgan, Paul W. Coteus, Robert L. Wisnieff
  • Method of producing a land grid array (LGA) interposer utilizing metal-on-elastomer
    Patent number: 8752284
    Abstract: A method of producing a land grid array (LGA) interposer structure, including an electrically insulating carrier plane, and at least one interposer mounted on a first surface of said carrier plane. The interposer possesses a hemi-toroidal configuration in transverse cross-section and is constituted of a dielectric elastomeric material. A plurality of electrically-conductive elements are arranged about the surface of the at least one hemi-toroidal interposer and extend radically inwardly and downwardly from an uppermost end thereof into electrical contact with at least one component located on an opposite side of the electrically insulating carrier plane.
    Type: Grant
    Filed: March 13, 2008
    Date of Patent: June 17, 2014
    Assignee: International Business Machines Corporation
    Inventors: Gareth G. Hougham, Brian S. Beaman, Evan G. Colgan, Paul W. Coteus, Stefano S. Oggioni, Enrique Vargas
  • COLLECTIVE NETWORK FOR COMPUTER STRUCTURES
    Publication number: 20140122980
    Abstract: A system and method for enabling high-speed, low-latency global collective communications among interconnected processing nodes. The global collective network optimally enables collective reduction operations to be performed during parallel algorithm operations executing in a computer structure having a plurality of the interconnected processing nodes. Router devices are included that interconnect the nodes of the network via links to facilitate performance of low-latency global processing operations at nodes of the virtual network and class structures. The global collective network may be configured to provide global barrier and interrupt functionality in asynchronous or synchronized manner. When implemented in a massively-parallel supercomputing structure, the global collective network is physically and logically partitionable according to needs of a processing algorithm.
    Type: Application
    Filed: January 6, 2014
    Publication date: May 1, 2014
    Applicant: International Business Machines Corporation
    Inventors: Matthias A. Blumrich, Paul W. Coteus, Dong Chen, Alan Gara, Mark E. Giampapa, Philip Heidelberger, Dirk Hoenicke, Todd Takken, Burkhard Steinmacher-Burow, Pavlos M. Vranas
  • MEMORY SYSTEM CONNECTOR
    Publication number: 20140115281
    Abstract: According to one embodiment a memory system includes a circuit card and a separable area array connector on the circuit card. The system also includes a memory device positioned on the circuit card, wherein the memory device is configured to communicate with a main processor of a computer system via the area array connector.
    Type: Application
    Filed: October 22, 2012
    Publication date: April 24, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Paul W. Coteus, Shawn A. Hall, Hillery C. Hunter, Douglas J. Joseph, Charles A. Kilmer, Kyu-hyoun Kim, Warren E. Maule, Todd E. Takken
  • MEMORY DEVICE REFRESH
    Publication number: 20140071778
    Abstract: According to one embodiment of the present invention, a method for refreshing memory includes receiving a synchronization command at a memory device. An internal refresh timer is reset within the memory device based on receiving the synchronization command. An internal refresh trigger is generated within the memory device based on the internal refresh timer reaching a predetermined value. A refresh of a memory array is performed within the memory device based on the internal refresh trigger.
    Type: Application
    Filed: September 11, 2012
    Publication date: March 13, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Paul W. Coteus, Douglas J. Joseph, Kyu-hyoun Kim
  • Massively parallel supercomputer
    Patent number: 8667049
    Abstract: A novel massively parallel supercomputer of hundreds of teraOPS-scale includes node architectures based upon System-On-a-Chip technology, i.e., each processing node comprises a single Application Specific Integrated Circuit (ASIC). Within each ASIC node is a plurality of processing elements each of which consists of a central processing unit (CPU) and plurality of floating point processors to enable optimal balance of computational performance, packaging density, low cost, and power and cooling requirements. The plurality of processors within a single node individually or simultaneously work on any combination of computation or communication as required by the particular algorithm being solved. The system-on-a-chip ASIC nodes are interconnected by multiple independent networks that optimally maximizes packet communications throughput and minimizes latency.
    Type: Grant
    Filed: August 3, 2012
    Date of Patent: March 4, 2014
    Assignee: International Business Machines Corporation
    Inventors: Matthias A. Blumrich, Dong Chen, George L. Chiu, Thomas M. Cipolla, Paul W. Coteus, Alan G. Gara, Mark E. Giampap, Philip Heidlberger, Gerard V. Kopcsay, Lawrence S. Mok, Todd E. Takken
  • Advanced memory device having improved performance, reduced power and increased reliability
    Patent number: 8659959
    Abstract: An advanced memory having improved performance, reduced power and increased reliability. A memory device includes a memory array, a receiver for receiving a command and associated data, error control coding circuitry for performing error control checking on the received command, and data masking circuitry for preventing the associated data from being written to the memory array in response to the error control coding circuitry detecting an error in the received command. Another memory device includes a programmable preamble. Another memory device includes a fast exit self-refresh mode. Another memory device includes auto refresh function that is controlled by the characteristic device. Another memory device includes an auto refresh function that is controlled by a characteristic of the memory device.
    Type: Grant
    Filed: August 6, 2012
    Date of Patent: February 25, 2014
    Assignee: International Business Machines Corporation
    Inventors: Kyu-Hyoun Kim, George L. Chiu, Paul W. Coteus, Daniel M. Dreps, Kevin C. Gower, Hillery C. Hunter, Charles A. Kilmer, Warren E. Maule
  • T-STAR INTERCONNECTION NETWORK TOPOLOGY
    Publication number: 20140044015
    Abstract: According to one embodiment of the present invention, a method of constructing network communication for a grid of node groups is provided, the grid including an M dimensional grid, each node group including N nodes, wherein M is greater than or equal to one and N is greater than one, wherein each node includes a router. The method includes directly connecting each node in each node group to every other node in the node group via intra-group links and directly connecting each node in each node group of the M dimensional grid to a node in each neighboring node group in the M dimensional grid via inter-group links.
    Type: Application
    Filed: August 13, 2012
    Publication date: February 13, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Dong Chen, Paul W. Coteus, Noel A. Eisley, Philip Heidelberger, Robert M. Senger, Yutaka Sugawara
  • T-STAR INTERCONNECTION NETWORK TOPOLOGY
    Publication number: 20140044006
    Abstract: According to one embodiment of the present invention, a system for network communication includes an M dimensional grid of node groups, each node group including N nodes, wherein M is greater than or equal to one and N is greater than one and each node comprises a router and intra-group links directly connecting each node in each node group to every other node in the node group. In addition, the system includes inter-group links directly connecting each node in each node group to a node in each neighboring node group in the M dimensional grid.
    Type: Application
    Filed: August 8, 2012
    Publication date: February 13, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Dong Chen, Paul W. Coteus, Noel A. Eisley, Philip Heidelberger, Robert M. Senger, Yutaka Sugawara
  • Collective network for computer structures
    Patent number: 8626957
    Abstract: A system and method for enabling high-speed, low-latency global collective communications among interconnected processing nodes. The global collective network optimally enables collective reduction operations to be performed during parallel algorithm operations executing in a computer structure having a plurality of the interconnected processing nodes. Router devices are included that interconnect the nodes of the network via links to facilitate performance of low-latency global processing operations at nodes of the virtual network. The global collective network may be configured to provide global barrier and interrupt functionality in asynchronous or synchronized manner. When implemented in a massively-parallel supercomputing structure, the global collective network is physically and logically partitionable according to needs of a processing algorithm.
    Type: Grant
    Filed: May 5, 2011
    Date of Patent: January 7, 2014
    Assignee: International Business Machines Corporation
    Inventors: Matthias A. Blumrich, Paul W. Coteus, Dong Chen, Alan Gara, Mark E. Giampapa, Philip Heidelberger, Dirk Hoenicke, Todd E. Takken, Burkhard D. Steinmacher-Burow, Pavlos M. Vranas
  • IMPLEMENTING TIMING ALIGNMENT AND SYNCHRONIZED MEMORY ACTIVITIES OF MULTIPLE MEMORY DEVICES ACCESSED IN PARALLEL
    Publication number: 20130332680
    Abstract: A method and circuit for implementing synchronized memory activities of multiple memory devices being accessed in parallel, and a design structure on which the subject circuit resides are provided. Each memory circuit generates an internal status signal for predefined internal memory activities and provides an output signal coupled to the multiple memory devices. Each memory circuit monitors the generated internal status signal and the output signal of at least one of the multiple memory devices, and responsive to the monitored signals generates a control signal for adjusting operation of its memory activities to synchronize memory activities of the memory devices.
    Type: Application
    Filed: June 12, 2012
    Publication date: December 12, 2013
    Applicant: International Business Machines Corporation
    Inventors: Paul W. Coteus, Kyu-hyoun Kim
  • Reproducibility in a multiprocessor system
    Patent number: 8595554
    Abstract: Fixing a problem is usually greatly aided if the problem is reproducible. To ensure reproducibility of a multiprocessor system, the following aspects are proposed: a deterministic system start state, a single system clock, phase alignment of clocks in the system, system-wide synchronization events, reproducible execution of system components, deterministic chip interfaces, zero-impact communication with the system, precise stop of the system and a scan of the system state.
    Type: Grant
    Filed: May 5, 2010
    Date of Patent: November 26, 2013
    Assignee: International Business Machines Corporation
    Inventors: Ralph A. Bellofatto, Dong Chen, Paul W. Coteus, Noel A. Eisley, Alan Gara, Thomas M. Gooding, Rudolf A. Haring, Philip Heidelberger, Gerard V. Kopcsay, Thomas A. Liebsch, Martin Ohmacht, Don D. Reed, Robert M. Senger, Burkhard Steinmacher-Burow, Yutaka Sugawara