Abstract: A memory device comprising a memory cell array; an input circuit providing drive signals to the memory cell array dependent on externally received command data; an output buffer buffering data read out from the memory cell array; and a timer driving the output buffer such that the buffered data are provided at an output after an adjustable time interval has elapsed, the adjustable time interval beginning with the provision of the drive signals.

Abstract: A control unit is set up to generate and output periodic clock signals, that are in sync with and at the same frequency as a periodic basic clock that is input into it, and periodic control signals, that are likewise in sync with the basic clock, and to turn on/turn off output of at least the clock signal in reaction to an activation/deactivation signal, which is routed to it externally, to a synchronous parallel/serial converter executing synchronization and serialization of a parallel data signal with the basic clock. Whereas output of the clock signal and optionally of the control signals are turned off, immediately after the activation/deactivation signal has assumed its deactivation state, the control unit is able to synchronize turning control signals on again, when the activation/deactivation signal has assumed its activation state.

Abstract: A memory device comprising a memory cell array; an input circuit for receiving command data and providing drive signals to the memory cell array; an output buffer for buffering data read out from the memory cell array; and a timer for driving the output buffer such that the buffered data are provided at an output after a predetermined time interval has elapsed, the predetermined time interval beginning with the provision of the drive signals.

Abstract: A semiconductor memory chip includes: a reception interface section for receiving external data, command, and address signals in form of serial signal frames; an intermediate data buffer for intermediately storing write data and, optionally, write data mask bits to be written to a memory cell array; a memory core having a bank organized memory cell array; a decoder section for decoding an address derived from a signal frame received from the reception interface section for writing/reading data in/from one or more memory banks of the memory cell array in accordance with a write/read command within one or more received signal frames; and a frame decoder provided as an interface between the reception interface section and the memory core for decoding one or more commands included in one or more frames and outputting data addresses, command, and read/write access indication signals to the memory core and to the intermediate data buffer.

Abstract: A memory arrangement includes an interface configured to transmit coding and/or decoding data in the form of data packets in accordance with a predefined protocol. The memory arrangement includes at least two memory banks, each memory bank including at least one memory cell. The memory arrangement includes at least two memory-bank access devices configured to facilitate accessing, the data of the at least one memory cell of each of the at least two memory banks. The memory arrangement includes at least two temporary storage devices configured to temporarily store data being transmitted between the interface and the at least two memory-bank access devices. Each of the at least two temporary storage devices is connected to the interface and to one of the at least two memory-bank access devices.

Abstract: A memory arrangement includes an interface configured to transmit data in the form of data packets according to a predefined protocol. The memory arrangement includes at least two memory banks. Each memory bank includes at least one memory cell. The memory arrangement includes at least two memory bank access devices configured to facilitate accessing the data of the at least one memory cell of each of the at least two memory banks. The memory arrangement includes at least two data packet processing devices configured to encode and/or decode the data packets. The at least two data packet processing devices are assigned to different memory bank access devices.

Abstract: A synchronous parallel/serial converter is disclosed. In one embodiment, the a synchronous parallel/serial converter that receives a parallel n-bit input signal and comprising a first shift register that receives an odd-numbered part of the input signal with a first load signal in synchronism with a clock signal having a clock rate half the clock rate of a system clock, and provides a serial output as a first one-bit signal sequence; a second shift register that receives an even-numbered part of the input signal with a second load signal synchronism with the clock signal and provides a serial output as a second one-bit signal sequence; and a fusion unit that fuses the first serial one-bit signal sequence synchronously with the clock signal and the second serial one-bit signal sequence in synchronism the clock signal to form a serial one-bit output signal.

Abstract: A semiconductor memory chip includes: a reception interface section for receiving external data, command, and address signals in form of serial signal frames; an intermediate data buffer for intermediately storing write data and, optionally, write data mask bits to be written to a memory cell array; a memory core having a bank organized memory cell array; a decoder section for decoding an address derived from a signal frame received from the reception interface section for writing/reading data in/from one or more memory banks of the memory cell array in accordance with a write/read command within one or more received signal frames; and a frame decoder provided as an interface between the reception interface section and the memory core for decoding one or more commands included in one or more frames and outputting data addresses, command, and read/write access indication signals to the memory core and to the intermediate data buffer.

Abstract: Method and apparatus for communication (e.g., transmitting and/or receiving) command, address and data signals from a memory device to a memory controller or vice versa. The data signals are transferred with a first rate and command signals and/or address signals are transferred with a second rate lower than a first rate. Additionally or alternatively a command sequence code identifying a command sequence from a predefined group of command sequences is transferred with the first or with the second rate.

Abstract: A semiconductor memory chip includes: a reception interface section for receiving external data, command, and address signals in form of serial signal frames; an intermediate data buffer for intermediately storing write data and, optionally, write data mask bits to be written to a memory cell array; a memory core having a bank organized memory cell array; a decoder section for decoding an address derived from a signal frame received from the reception interface section for writing/reading data in/from one or more memory banks of the memory cell array in accordance with a write/read command within one or more received signal frames; and a frame decoder provided as an interface between the reception interface section and the memory core for decoding one or more commands included in one or more frames and outputting data addresses, command, and read/write access indication signals to the memory core and to the intermediate data buffer.

Abstract: A semiconductor memory chip in which signals are transferred as serial signal frames includes a frame decoder providing an interface between a memory core and a reception interface. The frame decoder includes a command type decoder for decoding the types of commands included in frames according to the decoded type of the commands, a memory command evaluator/generator for scheduling and preparing single commands for the core, an intermediate data buffer command evaluator/generator for scheduling and preparing control signals for an intermediate data buffer, and a system command evaluator/generator for preparing and scheduling system commands. These system commands provide timing parameters to ensure time intervals between consecutive commands within one frame or between frames and are stored in a system mode register. The operation of the frame decoder is edge-synchronized by a frame clock or a synchronization decoder clock signal which is phase-aligned to that frame clock signal.

Abstract: In a semiconductor memory system, the memory chips are linked to a memory module in a shared loop forward architecture and connected in a point-to-point connection to a memory controller. Each memory chip includes a high-speed interface circuit including: a read and write data/command-and-address signal re-driver/transmitter path for re-driving serial read data and write data/command-and-address signals not destined for the semiconductor memory chip; and a main signal path which includes a serial-to-parallel converter and a synchronizer for serial-to-parallel converting and synchronizing with a reference clock signal write data/command-and-address signals destined for the semiconductor memory chip as well as a parallel-to-serial converter for parallel-to-serial converting read data signals read from a memory core of the memory chips, and a switch for inserting the parallel-to-serial converted read data signals into the re-driver/transmitter path.

Abstract: A method for transferring data into a data memory using a data protocol is presented. The data memory is an error correction code (ECC) memory or a non-error correction code memory. The data protocol has different frames. When data are written into an ECC memory, the protocol includes a data mask frame in which the data mask bits are replaced by ECC bits. The method is designed such that ECC and non-ECC DRAMs can be established with the same protocol and at least a similar architecture.

Abstract: In a semiconductor memory chips, a semiconductor memory system, and a method of masking write data, data, command, and address signal streams are serially transmitted in the form of signal frames in accordance with a predefined protocol. The semiconductor memory system and predefined protocol are adapted to transfer write data mask bits in a close relation to respectively associated write data units within one write data/command stream. An interface section between a reception interface and a memory core of the semiconductor memory chip includes a frame decoder and a intermediate data buffer.

Abstract: A semiconductor memory system includes a semiconductor memory chip in which data, command, and address signals are transmitted serially between a memory controller and the semiconductor memory chip in signal frames in correspondence with a predetermined protocol. In a receive signal path within the semiconductor memory chip, a frame decoder for decoding the signal frames is arranged following a receiving interface device, and between the frame decoder and a memory core, an intermediate storage device is arranged which has a cell array including a multiplicity of memory cells, and an addressing and selector circuit to which address signals decoded by the frame decoder from command and/or write signal frames supplied by the memory controller are applied, for addressing the cell array and for selecting the write data to be written into the cell array and to be read out of the cell array.

Abstract: A high-speed interface circuit is implemented in a semiconductor memory chip including a memory core, a first interface circuit section, and a second interface circuit section. The first interface circuit section is connectable to a write data-/command and address signal bus, includes a write data-/command and address re-driver/transmitter path (which may be transparent) and does not include any clock signal synchronizing circuitry, and a main write signal path including a serial-to-parallel converting and synchronizing device to synchronize with a reference clock signal received write data-/command and address signals and delivering the parallel converted write signals to the memory core.

Abstract: One embodiment of the present invention provides to a memory device adapted to receive data according to a write clock signal and to output data according to a read clock signal, comprising a clock port configured to output the read clock signal and to receive the write clock signal and a serial bidirectional driver configured to output the read clock signal via the clock port and to receive the write clock signal via the clock port simultaneously.

Abstract: The present invention relates to a memory system having a memory device with two clock lines. One embodiment of the present invention provides a memory system comprising at least one memory device, a memory controller to control operation of the memory device, a first clock line which extends from a write clock output of the memory controller to a clock port of the memory device to provide a clock signal to the memory device, and a second clock line which extends from the clock port of the memory device to a read clock input of the memory controller to forward the clock signal applied to the clock port of the memory device back to a read clock input of the memory controller. The memory device may further comprise a synchronization circuit adapted to receive the clock signal from the memory controller and to, provide an output data synchronized to the forwarded clock signal.

Abstract: In a semiconductor memory system having a loop forward architecture, the command, address and write data stream and the separate read data stream in form of protocol-based frames transmitted to/from memory chips in the following order: memory controller to the first memory chip, to the second memory chip, to the third memory chip and to the fourth memory chip and the read data stream is transferred from the fourth memory chip to the memory controller. With each command usually one of four memory chips is accessed for data processing, while three of four memory chips have only to fulfil a simple re-drive of CAwD stream and read data stream stream. By separately transferring a rank select signal not embedded in the frame from the memory controller to each memory chip a lot of more flexibility for these tasks can be achieved.

Abstract: A synchronous signal generator is provided that contains a first and second counting and delay circuit, which both are in a subhierarchical position with respect to a reset signal synchronization/delay circuit. The reset signal synchronization/delay circuit and the first and second counting and delay circuit are triggered by a basic clock signal or a first clock signal derived therefrom to be identical in frequency and phase, and contain counting means whose initial and final counting state are adjustable in order to set, in a clocked fashion, the temporal positions of a first and second load signal that are output by the first counting and delay circuit as well as of a FIFO read clock signal that is output by the second counting and delay circuit and thus adapt them to the temporal requirements of a semiconductor memory system containing the synchronous signal generator.