Patents by Inventor Peter Deane

Peter Deane has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20130010834
    Abstract: Systems and methods for use in CDMA antenna systems are provided in which signals each having a common overhead component are transmitted on a set of adjacent beams of a sector with a micro-timing offset between signals transmitted on adjacent pairs of beams which is large enough that destructive cancellation substantially does not occur between the pair of beams.
    Type: Application
    Filed: July 9, 2012
    Publication date: January 10, 2013
    Inventors: Abdelgader Legnain, Peter Deane, Neil M. McGowan
  • Patent number: 8340724
    Abstract: The present invention allows transmission of multiple signals between masthead electronics and base housing electronics in a base station environment. At least some of the received signals from the multiple antennas are translated to being centered about different center frequencies, such that the translated signals may be combined into a composite signal including each of the received signals. The composite signal is then sent over a single feeder cable to base housing electronics, wherein the received signals are separated and processed by transceiver circuitry. Prior to being provided to the transceiver circuitry, those signals that were translated from being centered about one frequency to another may be retranslated to being centered about the original center frequency.
    Type: Grant
    Filed: November 14, 2011
    Date of Patent: December 25, 2012
    Assignee: Apple Inc.
    Inventors: Steve Beaudin, Keith Russell Edwards, Xiaoyun Hu, Peter Deane
  • Patent number: 8305722
    Abstract: A two terminal ESD protection structure formed by an alternating arrangement of adjacent p-n-p-n-p semiconductor regions provides protection against both positive and negative ESD pulses. When an ESD pulse appears across the two terminals of the ESD protection structure, one of the inherent n-p-n-p thyristors is triggered into a snap-back mode thereby to form a low impedance path to discharge the ESD current. Some embodiments of the ESD protection structure of the present invention have an enhanced current handling capability and are formed by combining a number of standard cells. The standard cells include a corner cell, a center cell and an edge cell which are arranged adjacent each other to form an ESD protection structure which provides for current flow from across many locations therein. Some embodiments of the ESD protection structure of the present invention include a network consisting of a pair of current sources, e.g.
    Type: Grant
    Filed: March 28, 2011
    Date of Patent: November 6, 2012
    Assignee: National Semiconductor Corporation
    Inventors: Albert Z. H. Wang, Chen H. Tsay, Peter Deane
  • Patent number: 8238977
    Abstract: Systems and methods for use in CDMA antenna systems are provided in which signals each having a common overhead component are transmitted on a set of adjacent beams of a sector with a micro-timing offset between signals transmitted on adjacent pairs of beams which is large enough that destructive cancellation substantially does not occur between the pair of beams.
    Type: Grant
    Filed: May 26, 2011
    Date of Patent: August 7, 2012
    Assignee: Apple Inc.
    Inventors: Abdelgader Legnain, Peter Deane, Neil M. McGown
  • Publication number: 20120182659
    Abstract: A two terminal ESD protection structure formed by an alternating arrangement of adjacent p-n-p-n-p semiconductor regions provides protection against both positive and negative ESD pulses. When an ESD pulse appears across the two terminals of the ESD protection structure, one of the inherent n-p-n-p thyristors is triggered into a snap-back mode thereby to form a low impedance path to discharge the ESD current. Some embodiments of the ESD protection structure of the present invention have an enhanced current handling capability and are formed by combining a number of standard cells. The standard cells include a corner cell, a center cell and an edge cell which are arranged adjacent each other to form an ESD protection structure which provides for current flow from across many locations therein. Some embodiments of the ESD protection structure of the present invention include a network consisting of a pair of current sources, e.g.
    Type: Application
    Filed: March 28, 2011
    Publication date: July 19, 2012
    Inventors: Albert Z. H. Wang, Chen H. Tsay, Peter Deane
  • Publication number: 20120076019
    Abstract: Methods and devices for removing cross coupling effects between elements of an antenna array (110) are provided. Cross coupling coefficients between all pairs of antenna elements of the antenna array are predetermined to minimize a total power in theoretical null points calculated without considering the cross element effects. A transceiver (100) includes a multiplexing block (105) configured to receive data signals to be transmitted via the antenna elements and to output to at least one of the antenna elements, a sum signal including (i) a data signal, which data signal is designated for the at least one antenna element, and (ii) a linear combination of data signals designated for other antenna elements of the antenna array, each of the data signals in the linear combination being weighted by a respective cross coupling coefficient between the at least one antenna element and an antenna element emitting the each of the data signals.
    Type: Application
    Filed: September 24, 2010
    Publication date: March 29, 2012
    Applicant: TELEFONAKTIEBOLAGET L M ERICSSON (PUBL)
    Inventors: Neil McGowan, Peter Deane
  • Publication number: 20120058720
    Abstract: The present invention allows transmission of multiple signals between masthead electronics and base housing electronics in a base station environment. At least some of the received signals from the multiple antennas are translated to being centered about different center frequencies, such that the translated signals may be combined into a composite signal including each of the received signals. The composite signal is then sent over a single feeder cable to base housing electronics, wherein the received signals are separated and processed by transceiver circuitry. Prior to being provided to the transceiver circuitry, those signals that were translated from being centered about one frequency to another may be retranslated to being centered about the original center frequency.
    Type: Application
    Filed: November 14, 2011
    Publication date: March 8, 2012
    Applicant: ROCKSTAR BIDCO, LP
    Inventors: Steve Beaudin, Keith Russell Edwards, Xiaoyun Hu, Peter Deane
  • Publication number: 20120001801
    Abstract: A beamformer is arranged to receive an input from a first antenna element and from at least one other antenna element and to generate at least a first and second output beam. The first and second output beams are combined at a connecting port such that signals received at the first antenna element are constructively combined at the connecting port and signals received at another antenna element or elements are destructively combined at the connecting port, so that a receiver connected to the connecting port may receive signals from the first antenna element and may not receive signals from the other antenna element or elements. The arrangement may also be used to transmit a signal which is fed into the connecting point from the first antenna element and not from the other antenna element or elements.
    Type: Application
    Filed: September 13, 2011
    Publication date: January 5, 2012
    Applicant: ROCKSTAR BIDCO L.P.
    Inventors: David Neil Adams, Peter Deane, Steven Raymond Hall
  • Patent number: 8063822
    Abstract: A beamformer is arranged to receive an input from a first antenna element and from at least one other antenna element and to generate at least a first and second output beam. The first and second output beams are combined at a connecting port such that signals received at the first antenna element are constructively combined at the connecting port and signals received at another antenna element or elements are destructively combined at the connecting port, so that a receiver connected to the connecting port may receive signals from the first antenna element and may not receive signals from the other antenna element or elements. The arrangement may also be used to transmit a signal which is fed into the connecting point from the first antenna element and not from the other antenna element or elements.
    Type: Grant
    Filed: June 25, 2008
    Date of Patent: November 22, 2011
    Assignee: Rockstar Bidco L.P.
    Inventors: David Neil Adams, Peter Deane, Steven Raymond Hall
  • Patent number: 8060147
    Abstract: The present invention allows transmission of multiple signals between masthead electronics and base housing electronics in a base station environment. At least some of the received signals from the multiple antennas are translated to being centered about different center frequencies, such that the translated signals may be combined into a composite signal including each of the received signals. The composite signal is then sent over a single feeder cable to base housing electronics, wherein the received signals are separated and processed by transceiver circuitry. Prior to being provided to the transceiver circuitry, those signals that were translated from being centered about one frequency to another may be retranslated to being centered about the original center frequency.
    Type: Grant
    Filed: April 27, 2010
    Date of Patent: November 15, 2011
    Assignee: Nortel Networks Limited
    Inventors: Steve Beaudin, Keith Russell Edwards, Xiaoyun Hu, Peter Deane
  • Publication number: 20110235683
    Abstract: Systems and methods for use in CDMA antenna systems are provided in which signals each having a common overhead component are transmitted on a set of adjacent beams of a sector with a micro-timing offset between signals transmitted on adjacent pairs of beams which is large enough that destructive cancellation substantially does not occur between the pair of beams.
    Type: Application
    Filed: May 26, 2011
    Publication date: September 29, 2011
    Applicant: Nortel Networks Limited
    Inventors: Abdelgader Legnain, Peter Deane, Neil M. McGowan
  • Patent number: 7953446
    Abstract: Systems and methods for use in CDMA antenna systems are provided in which signals each having a common overhead component are transmitted on a set of adjacent beams of a sector with a micro-timing offset between signals transmitted on adjacent pairs of beams which is large enough that destructive cancellation substantially does not occur between the pair of beams.
    Type: Grant
    Filed: November 3, 2003
    Date of Patent: May 31, 2011
    Assignee: Nortel Networks Limited
    Inventors: Abdelgader Legnain, Peter Deane, Neil M. McGowan
  • Publication number: 20110115071
    Abstract: Various apparatuses and methods for forming integrated circuit packages are described. One aspect of the invention pertains to an integrated circuit package in which one or more integrated circuits are embedded in a substrate and covered with a layer of photo-imageable epoxy. The substrate can be made of various materials, including silicon, quartz and glass. An integrated circuit is positioned within a cavity in the top surface of the substrate. The epoxy layer is formed over the top surface of the substrate and the active face of the integrated circuit. An interconnect layer is formed over the epoxy layer and is electrically coupled with the integrated circuit.
    Type: Application
    Filed: January 25, 2011
    Publication date: May 19, 2011
    Applicant: NATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Peter Smeys, Peter Johnson, Peter Deane, Reda R. Razouk
  • Publication number: 20110111760
    Abstract: The invention relates to a method and apparatus for determining whether two user equipments (UEs) in a wireless network can be co-scheduled by an uplink scheduler. The method includes the determination of orthogonality factors for each pair of equipments to be considered and, from the orthogonality factors, selecting UEs to be co-scheduled.
    Type: Application
    Filed: November 9, 2009
    Publication date: May 12, 2011
    Inventors: David Bevan, Simon Gale, Julius Robson, Peter Deane
  • Patent number: 7936020
    Abstract: A two-terminal ESD protection structure formed by an arrangement of five adjacent semiconductor regions (112, 114, 116, 118, and 120) of alternating conductivity type provides protection against both positive and negative ESD voltages. The middle semiconductor region electrically floats. When the two terminals (A and K) of the ESD protection structure are subjected to an ESD voltage, the structure goes into operation by triggering one of its two inherent thyristors (170 and 180) into a snap-back mode that provides a low impedance path through the structure for discharging the ESD current.
    Type: Grant
    Filed: August 2, 2007
    Date of Patent: May 3, 2011
    Assignee: National Semiconductor Corporation
    Inventors: Albert Z. H. Wang, Chen H. Tsay, Peter Deane
  • Patent number: 7901984
    Abstract: Various apparatuses and methods for forming integrated circuit packages are described. One aspect of the invention pertains to a method for forming a microsystem and one or more passive devices in the microsystem. Layers of epoxy are sequentially deposited over a substrate to form multiple planarized layers of epoxy over the substrate. The epoxy layers are deposited by spin coating. At least some of the epoxy layers are photolithographically patterned after they are deposited and before the next epoxy layer is deposited. An integrated circuit having multiple I/O bond pads is placed on an associated epoxy layer. At least one conductive interconnect layer is formed over an associated epoxy layer. A passive component is formed within at least one of the epoxy layers. The passive component is electrically coupled with the integrated circuit via at least one of the interconnect layers. Multiple external package contacts are formed.
    Type: Grant
    Filed: June 5, 2009
    Date of Patent: March 8, 2011
    Assignee: National Semiconductor Corporation
    Inventors: Peter Smeys, Peter Johnson, Peter Deane
  • Patent number: 7901981
    Abstract: Various methods for forming an integrated circuit micro-module are described. In one aspect of the invention, layers of an epoxy are sequentially deposited over a substrate to form planarized layers of epoxy over the substrate. The epoxy layers are deposited using spin coating. At least some of the layers are photolithographically patterned after they are deposited and before the next epoxy layer is deposited. Openings are formed in at least some of the patterned epoxy layers after they are patterned and before the next epoxy layer is deposited. An integrated circuit is placed within one of the openings. At least one of the epoxy layers is deposited after the placement of the integrated circuit to cover the integrated circuit. At least one conductive interconnect layer is formed over an associated epoxy layer. Multiple external package contacts are formed.
    Type: Grant
    Filed: June 5, 2009
    Date of Patent: March 8, 2011
    Assignee: National Semiconductor Corporation
    Inventors: Peter Smeys, Peter Johnson, Peter Deane
  • Patent number: 7902661
    Abstract: Various apparatuses and methods for forming integrated circuit packages are described. One aspect of the invention pertains to an integrated circuit package in which one or more integrated circuits are embedded in a substrate and covered with a layer of photo-imageable epoxy. The substrate can be made of various materials, including silicon, quartz and glass. An integrated circuit is positioned within a cavity in the top surface of the substrate. The epoxy layer is formed over the top surface of the substrate and the active face of the integrated circuit. An interconnect layer is formed over the epoxy layer and is electrically coupled with the integrated circuit.
    Type: Grant
    Filed: December 21, 2009
    Date of Patent: March 8, 2011
    Assignee: National Semiconductor Corporation
    Inventors: Peter Smeys, Peter Johnson, Peter Deane, Reda R. Razouk
  • Patent number: 7898068
    Abstract: Various apparatus and methods for improving the dissipation of heat from integrated circuit micro-modules are described. One aspect of the invention pertains to an integrated circuit package with one or more thermal pipes. In this aspect, the integrated circuit package includes multiple layers of a cured, planarizing dielectric. An electrical device is embedded within at least one of the dielectric layers. At least one electrically conductive interconnect layer is embedded within one or more of the dielectric layers. A thermal pipe made of a thermally conductive material is embedded in at least one associated dielectric layer. The thermal pipe thermally couples the electrical device with one or more external surfaces of the integrated circuit package. Various methods for forming the integrated circuit package are described.
    Type: Grant
    Filed: June 5, 2009
    Date of Patent: March 1, 2011
    Assignee: National Semiconductor Corporation
    Inventors: Peter Smeys, Peter Johnson, Peter Deane
  • Patent number: 7842544
    Abstract: Various apparatuses and methods for forming integrated circuit packages are described. One aspect of the invention pertains to a wafer level method for packaging micro-systems. A substrate prefabricated with metal vias can be provided. The substrate can also be made by forming holes in a substrate and electroplating an electrically conductive material into the holes to form the vias. Multiple microsystems are formed on a top surface of the substrate. Each microsystem is formed to include multiple layers of planarizing, photo-imageable epoxy, one or more interconnect layers and an integrated circuit. Each interconnect layer is embedded in an associated epoxy layer. The integrated circuit is positioned within at least an associated epoxy layer. The interconnect layers of the microsystems are formed such that at least some of the interconnect layers are electrically coupled with one or more of the metal vias in the substrate.
    Type: Grant
    Filed: June 5, 2009
    Date of Patent: November 30, 2010
    Assignee: National Semiconductor Corporation
    Inventors: Peter Smeys, Peter Johnson, Peter Deane