Abstract: A memory device includes core memory such as flash memory for storing data. The memory device includes a first power input to receive a first voltage used to power the flash memory. Additionally, the memory device includes a second power input to receive a second voltage. The memory device includes power management circuitry configured to receive the second voltage and derive one or more internal voltages. The power management circuitry supplies or conveys the internal voltages to the flash memory. The different internal voltages generated by the power management circuitry (e.g., voltage converter circuit) and supplied to the core memory enable operations such as read/program/erase with respect to cells in the core memory.

Abstract: Apparatus and methods for carrying out operations in a non-volatile memory cell having multiple memory states are disclosed. One of the methods is a method for programming N bits in a non-volatile memory cell configured to store up to N+1 bits, where N is an integer greater than zero. The method for programming includes programming N bits of data in the cell. The method for programming also includes programming an additional bit of data that is a logical function of the N bits of data in the cell. The cell is configured to provide 2N+1 threshold voltage ranges for bit storage and, in accordance with the logical function: i) a first set of 2N threshold voltage ranges of the 2N+1 threshold voltage ranges are used to store the N bits of data; and ii) a remaining second set of 2N threshold voltage ranges alternating with the first set are unused.

Abstract: A semiconductor device includes a bridging device having an external data interface, an external status interface, and a plurality of internal data interfaces. A plurality of memory devices are each connected to the bridging device via one of the internal data interfaces. Each of the memory devices has a ready/busy output connected to an input of the bridging device. The bridging device is configured to output a current state of each ready/busy output in a packetized format on the external status interface in response to a status request command received on the external status interface; and read information from a status register of a selected memory device over one of the internal data interfaces and provide the information on the external data interface in response to a status read command received on the external data interface. A method of operating a semiconductor device is also disclosed.

Abstract: A configurable memory subsystem includes a memory module with a circuit board having a first and a second memory-containing device (MCD) pair mounted thereto. Each MCD pair has a first MCD in communication with a second MCD. Each MCD has an input port, an output port, and a memory each communicating with a bridge. In response to a command, the bridge transfers at least one of a portion of a data packet from the input port to the output port or to the memory, or transfers a portion of a memory packet from the memory to the output port. A loop-back device receives the command and the data packet form the first MCD pair and transmits the command and data packet to the second MCD pair.

Abstract: A semiconductor device has a plurality of stacked semiconductor dice mounted on a substrate. Each die has similar dimensions. Each die has a first plurality of bonding pads arranged along a bonding edge of the die. A first group of the dice are mounted to the substrate with the bonding edge oriented in a first direction. A second group of the dice are mounted to the substrate with the bonding edge oriented in a second direction opposite the first direction. Each die is laterally offset in the second direction relative to the remaining dice by a respective lateral offset distance such that the bonding pads of each die are not disposed between the substrate and any portion of the remaining dice in a direction perpendicular to the substrate. A plurality of bonding wires connects the bonding pads to the substrate. A method of manufacturing a semiconductor device is also disclosed.

Abstract: A configurable memory subsystem includes a memory module with a circuit board having a first and a second memory-containing device (MCD) pair mounted thereto. Each MCD pair has a first MCD in communication with a second MCD. Each MCD has an input port, an output port, and a memory each communicating with a bridge. In response to a command, the bridge transfers at least one of a portion of a data packet from the input port to the output port or to the memory, or transfers a portion of a memory packet from the memory to the output port. A loop-back device receives the command and the data packet form the first MCD pair and transmits the command and data packet to the second MCD pair.

Abstract: In a semiconductor device having a terminal connected to an internal portion, a termination circuit for providing on-die termination for the terminal of the device. The termination circuit comprises a plurality of transistors, including at least one NMOS transistor and at least one PMOS transistor, connected between the terminal and a power supply; and control circuitry for driving a gate of each of NMOS transistor with a corresponding NMOS gate voltage and for driving a gate of each PMOS transistor with a corresponding PMOS gate voltage, the control circuitry being configured to control the NMOS and PMOS gate voltages so as to place the transistors in an ohmic region of operation when on-die termination is enabled. The power supply supplies a voltage that is less than each said NMOS gate voltage and greater than each said PMOS gate voltage.

Abstract: A memory device includes core memory such as flash memory for storing data. The memory device includes a first power input to receive a first voltage used to power the flash memory. Additionally, the memory device includes a second power input to receive a second voltage. The memory device includes power management circuitry configured to receive the second voltage and derive one or more internal voltages. The power management circuitry supplies or conveys the internal voltages to the flash memory. The different internal voltages generated by the power management circuitry (e.g., voltage converter circuit) and supplied to the core memory enable operations such as read/program/erase with respect to cells in the core memory.

Abstract: A DRAM system configured for high bandwidth communication, the system includes at least one DRAM having resistive termination devices within the DRAM, and a controller connected to the DRAM through a data bus. The controller includes resistive termination devices and the data bus includes at least one clock line driven intermittently. The data bus provides write data from the controller to the DRAM, and provides read data from the DRAM to the controller.

Abstract: This invention describes an improved high bandwidth chip-to-chip interface for memory devices, which is capable of operating at higher speeds, while maintaining error free data transmission, consuming lower power, and supporting more load. Accordingly, the invention provides a memory subsystem comprising at least two semiconductor devices; a main bus containing a plurality of bus lines for carrying substantially all data and command information needed by the devices, the semiconductor devices including at least one memory device connected in parallel to the bus; the bus lines including respective row command lines and column command lines; a clock generator for coupling to a clock line, the devices including clock inputs for coupling to the clock line; and the devices including programmable delay elements coupled to the clock inputs to delay the clock edges for setting an input data sampling time of the memory device.

Abstract: A memory device includes core memory such as flash memory for storing data. The memory device includes a first power input to receive a first voltage used to power the flash memory. Additionally, the memory device includes a second power input to receive a second voltage. The memory device includes power management circuitry configured to receive the second voltage and derive one or more internal voltages. The power management circuitry supplies or conveys the internal voltages to the flash memory. The different internal voltages generated by the power management circuitry (e.g., voltage converter circuit) and supplied to the core memory enable operations such as read/program/erase with respect to cells in the core memory.

Abstract: An arrangement of memory devices and a controller is based on an interface with a reduced pin count relative to a known memory device and controller arrangement. Facilitating the reduced pin count interface are some operations performed by the controller. The controller determines a width for a Data bus while assigning a target device address to each of the memory devices.

Abstract: In a semiconductor device having a terminal connected to an internal portion, a termination circuit for providing on-die termination for the terminal of the device. The termination circuit comprises a plurality of transistors, including at least one NMOS transistor and at least one PMOS transistor, connected between the terminal and a power supply; and control circuitry for driving a gate of each of NMOS transistor with a corresponding NMOS gate voltage and for driving a gate of each PMOS transistor with a corresponding PMOS gate voltage, the control circuitry being configured to control the NMOS and PMOS gate voltages so as to place the transistors in an ohmic region of operation when on-die termination is enabled. The power supply supplies a voltage that is less than each said NMOS gate voltage and greater than each said PMOS gate voltage.

Abstract: An arrangement of memory devices and a controller is based on an interface with a reduced pin count relative to a known memory device and controller arrangement. Facilitating the reduced pin count interface are some operations performed by the controller. The controller determines a width for a Data bus while assigning a target device address to each of the memory devices.

Abstract: A method of snap-shot data training to determine the optimum timing of the DQS enable signal in a single read operation is provided. This is accomplished by first writing a Gray code count sequence into the memory and then reading it back in a single burst. The controller samples the read burst at a fixed interval from the time the command was issued to determine the loop-around delay. A simple truth table lookup determines the optimum DQS enable timing for normal reads. Advantageously, during normal read operations, the first positive edge of the enabled DQS signal is used to sample a counter that is enabled every time a command is issued. If the counter sample changes, indicating timing drift has occurred, the DQS enable signal can be adjusted to compensate for the drift and maintain a position centered in the DQS preamble. This technique can also be applied to a system that uses the iterative approach to determining DQS enable timing on power up.

Abstract: In a semiconductor device having a terminal connected to an internal portion, a termination circuit for providing on-die termination for the terminal of the device. The termination circuit comprises a plurality of transistors, including at least one NMOS transistor and at least one PMOS transistor, connected between the terminal and a power supply; and control circuitry for driving a gate of each of NMOS transistor with a corresponding NMOS gate voltage and for driving a gate of each PMOS transistor with a corresponding PMOS gate voltage, the control circuitry being configured to control the NMOS and PMOS gate voltages so as to place the transistors in an ohmic region of operation when on-die termination is enabled. The power supply supplies a voltage that is less than each said NMOS gate voltage and greater than each said PMOS gate voltage.

Abstract: A semiconductor memory device including a plurality of memory die and a controller die. The controller die is connected to an internal control bus. The controller die is configured to provide to a selected one of the memory die an internal read command responsive to an external read command. The selected memory die is configured to provide read data to the controller in response to the internal read command; wherein latency between receipt by the controller die of the external read command and receipt of the read data from the selected memory die differs for at least two of the memory die when selected as the selected memory die.

Abstract: A memory device includes core memory such as flash memory for storing data. The memory device includes a first power input to receive a first voltage used to power the flash memory. Additionally, the memory device includes a second power input to receive a second voltage. The memory device includes power management circuitry configured to receive the second voltage and derive one or more internal voltages. The power management circuitry supplies or conveys the internal voltages to the flash memory. The different internal voltages generated by the power management circuitry (e.g., voltage converter circuit) and supplied to the core memory enable operations such as read/program/erase with respect to cells in the core memory.

Abstract: A method of snap-shot data training to determine the optimum timing of the DQS enable signal in a single read operation is provided. This is accomplished by first writing a Gray code count sequence into the memory and then reading it back in a single burst. The controller samples the read burst at a fixed interval from the time the command was issued to determine the loop-around delay. A simple truth table lookup determines the optimum DQS enable timing for normal reads. Advantageously, during normal read operations, the first positive edge of the enabled DQS signal is used to sample a counter that is enabled every time a command is issued. If the counter sample changes, indicating timing drift has occurred, the DQS enable signal can be adjusted to compensate for the drift and maintain a position centered in the DQS preamble. This technique can also be applied to a system that uses the iterative approach to determining DQS enable timing on power up.

Abstract: A configurable memory subsystem includes a memory module with a circuit board having a first and a second memory-containing device (MCD) pair mounted thereto. Each MCD pair has a first MCD in communication with a second MCD. Each MCD has an input port, an output port, and a memory each communicating with a bridge. In response to a command, the bridge transfers at least one of a portion of a data packet from the input port to the output port or to the memory, or transfers a portion of a memory packet from the memory to the output port. A loop-back device receives the command and the data packet form the first MCD pair and transmits the command and data packet to the second MCD pair.