Abstract: A semiconductor device having a self test circuit including an embedded dynamic random access memory array for storing data, a self test controller for internally generating test data patterns and expected resulting data and for comparing the expected resulting data with actual resulting data, test interface circuitry for loading the test data patterns into the memory and reading back the actual resulting data from the memory, means for selectively programming a voltage level to be applied to a selected cell plate of the memory according to predetermined test requirements and means for storing an address of a defective memory cell. In addition, the semiconductor device includes means for repairing a defective memory row or column in response to a signal received from the self test controller.

Abstract: A single chip display processor comprised of a dynamic random access memory (DRAM) for storing at least one of graphics and video pixel data, a pixel data unit (PDU) for processing the pixel data, integrated in the same integrated circuit (IC) chip as the DRAM, the IC chip further comprising a massively parallel bus for transferring blocks of pixel data at the same time from the DRAM to the PDU, whereby the PDU can process the blocks of pixel data for subsequent display of processed pixel data.

Abstract: An output pulse signal can be fabricated in an integrated circuit from an input signal. The output signal retains the desired pulse shape unaffected by jitter. A switched capacitor FIR filter is used to form the pulse shape, and then the clocking of the digital signals used to operate the pulse shaper is controlled to control the timing of different segments. The result is an output signal which has jitter but retains the desired pulse shape. Since a phase corrector which senses jitter can control the clocking, the output pulse shape is unaffected by jitter. The output pulse signal can be produced in an integrated circuit since switched capacitor pulse shapers are used, rather than a continuous time filter.

Abstract: A phase locked loop for synchronizing a local digital signal with an incoming data signal is described. Parallel phase and frequency detectors compare the local and incoming signals and generate control pulse signals for controlling the frequency of a voltage controlled oscillator which generates the local digital signal. Logic circuitry is included in both the phase and frequency detectors for adjusting the generated control pulse signals in the event of detection of elongated pulse widths of the incoming data signal, indicating one of either an absence of incoming data signal or a bipolar violation in the event the data signals are ASI encoded. The phase locked loop is characterized by quick pull-in time, large pull-in frequency range, accurate clocking and low cost.

Abstract: A symmetric finite impulse response filter for receiving a digital input signal and generates a filtered analog output signal for application to a balanced line, such as a tip and ring lead pair. Logic levels of predetermined symmetrical bit pairs of the digital input signal are detected and in response, predetermined corresponding capacitors are selectively switched between bias and reference voltages, thereby charging predetermined voltages proportional to the capacitances of the capacitors. The predetermined voltages are summed in an operational amplifier which, in response produces a filtered analog output signal. Individual capacitors are utilized for realizing each pair of symmetrical coefficients of the filter transfer function, resulting in considerable economy of size. A switched capacitor implementation results in high speed performance, simple design and low cost.

Abstract: A decimating filter utilizing first and second switched input capacitors for sampling an input signal on opposite phases of a first sampling clock signal. The switched input capacitors are connected to an integrating circuit for filtering the sampling signal. An output of the integrating circuit is sampled according to a second sampling clock signal having a frequency equal to a submultiple of the first sampling clock signal frequency. By sampling the input signal on opposite phases, the input signal is effectively sampled at twice the first sampling clock signal frequency. Accordingly, in applications involving high sampling frequencies, such as digital signal transmission, the input signal can be sampled at a sufficiently high frequency without requiring a prohibitively high input sampling clock frequency. The decimating filter is of simple design and can be inexpensively implemented on an integrated circuit chip requiring small area.