Abstract: Transistors are provided that comprise a silicon carbide based semiconductor layer structure, a first current terminal, a second current terminal, a gate terminal, and a minimum gate terminal-to-second current terminal voltage clamp circuit in the semiconductor layer structure that is coupled between the gate terminal and the second current terminal.

Abstract: A semiconductor device includes a semiconductor layer structure comprising a source/drain region, a gate dielectric layer on the semiconductor layer structure, and a gate electrode on the gate dielectric layer. The source/drain region comprises a first portion comprising a first dopant concentration and a second portion comprising a second dopant concentration. The second portion is closer to a center of the gate electrode than the first portion.

Abstract: A transistor semiconductor die includes a first current terminal, a second current terminal, and a control terminal. A semiconductor structure is between the first current terminal, the second current terminal, and the control terminal and configured such that a resistance between the first current terminal and the second current terminal is based on a control signal provided at the control terminal. Short circuit protection circuitry is coupled between the control terminal and the second current terminal. In a normal mode of operation, the short circuit protection circuitry is configured to provide a voltage drop that is greater than a voltage of the control signal. In a short circuit protection mode of operation, the short circuit protection circuitry is configured to provide a voltage drop that is less than a voltage of the control signal.

Abstract: A transistor semiconductor die includes a first current terminal, a second current terminal, and a control terminal. A semiconductor structure is between the first current terminal, the second current terminal, and the control terminal and configured such that a resistance between the first current terminal and the second current terminal is based on a control signal provided at the control terminal. Short circuit protection circuitry is coupled between the control terminal and the second current terminal. In a normal mode of operation, the short circuit protection circuitry is configured to provide a voltage drop that is greater than a voltage of the control signal. In a short circuit protection mode of operation, the short circuit protection circuitry is configured to provide a voltage drop that is less than a voltage of the control signal.

Abstract: There is provided a micro electrical mechanical systems device package comprising: a first vacuum enclosure comprising a first enclosure wall; a micro electrical mechanical systems device being positioned within the first vacuum enclosure on a first side of the first enclosure wall; and a second vacuum enclosure, the second side of the first enclosure wall being within the second vacuum enclosure. Advantageously, the first vacuum enclosure is entirely within the second vacuum enclosure.

Abstract: A semiconductor device includes a semiconductor layer structure comprising a source/drain region, a gate dielectric layer on the semiconductor layer structure, and a gate electrode on the gate dielectric layer. The source/drain region comprises a first portion comprising a first dopant concentration and a second portion comprising a second dopant concentration. The second portion is closer to a center of the gate electrode than the first portion.

Abstract: A power semiconductor device includes a semiconductor layer structure and a protective overcoating on a bonding surface of the semiconductor layer structure. The bonding surface includes a plurality of adhesion features along an interface with the protective overcoating. The adhesion features protrude from and/or are recessed in the bonding surface, and define an adhesion strength between the bonding surface and the protective overcoating that spatially varies along the interface. Related devices and fabrication methods are also discussed.

Abstract: A semiconductor device includes a semiconductor layer structure comprising a source/drain region, a gate dielectric layer on the semiconductor layer structure, and a gate electrode on the gate dielectric layer. The source/drain region comprises a first portion comprising a first dopant concentration and a second portion comprising a second dopant concentration. The second portion is closer to a center of the gate electrode than the first portion.

Abstract: A semiconductor device includes a semiconductor layer structure comprising a source/drain region, a gate dielectric layer on the semiconductor layer structure, and a gate electrode on the gate dielectric layer. The source/drain region comprises a first portion comprising a first dopant concentration and a second portion comprising a second dopant concentration. The second portion is closer to a center of the gate electrode than the first portion.

Abstract: A semiconductor die includes a drift region, an active region in the drift region, and an edge termination region surrounding the active region in the drift region. The drift region has a first doping type. The edge termination region includes a charge compensation region, a number of guard rings, and a counter doping region. The charge compensation region is in the drift region and has a second doping type that is opposite the first doping type. The guard rings are in the charge compensation region, have the second doping type, and a doping concentration that is greater than a doping concentration of the charge compensation region. The counter doping region is in the drift region and overlaps at least a portion of the charge compensation region. The counter doping region has the first doping type.

Abstract: Structures that include semiconductor fins and methods for forming a structure that includes semiconductor fins. A first fin comprised of n-type semiconductor material and a second fin comprised of p-type semiconductor material are formed. A conductive strap is formed that couples an end of the first fin with an end of the second fin.

Abstract: One illustrative integrated circuit product disclosed herein comprises first and second spaced-apart P-active regions positioned on a buried insulation layer positioned on a base substrate, at least one first PFET transistor in the first P-active region, and a plurality of second PFET transistors in the second P-active region, wherein the first P-active region has a first length (in the gate length direction of the device) and the second P-active region has a second length that is greater than the first length and wherein the number of second PFET transistors is greater than the number of first PFET transistors. In this example, the product also includes a tensile-stressed layer of material positioned on the at least one first PFET transistor and above the first P-active region and a compressive-stressed layer of material positioned on the plurality of second PFET transistors and above the second P-active region.

Abstract: A transistor semiconductor die includes a first current terminal, a second current terminal, and a control terminal. A semiconductor structure is between the first current terminal, the second current terminal, and the control terminal and configured such that a resistance between the first current terminal and the second current terminal is based on a control signal provided at the control terminal. Short circuit protection circuitry is coupled between the control terminal and the second current terminal. In a normal mode of operation, the short circuit protection circuitry is configured to provide a voltage drop that is greater than a voltage of the control signal. In a short circuit protection mode of operation, the short circuit protection circuitry is configured to provide a voltage drop that is less than a voltage of the control signal.

Abstract: One illustrative integrated circuit product disclosed herein comprises first and second spaced-apart P-active regions positioned on a buried insulation layer positioned on a base substrate, at least one first PFET transistor in the first P-active region, and a plurality of second PFET transistors in the second P-active region, wherein the first P-active region has a first length (in the gate length direction of the device) and the second P-active region has a second length that is greater than the first length and wherein the number of second PFET transistors is greater than the number of first PFET transistors. In this example, the product also includes a tensile-stressed layer of material positioned on the at least one first PFET transistor and above the first P-active region and a compressive-stressed layer of material positioned on the plurality of second PFET transistors and above the second P-active region.

Abstract: Methods of locally changing the BOX layer of a MOSFET device to a high-k layer to provide different Vts with one backside voltage and the resulting device are provided. Embodiments include providing a Si substrate having a BOX layer formed over the substrate and a SOI layer formed over the BOX layer; implanting a high current of dopants into at least one portion of the BOX layer; performing a high-temperature anneal of the BOX layer; forming first and second fully depleted silicon-on-insulator (FDSOI) transistors on the SOI layer, the first FDSOI transistors formed above either the BOX layer or the at least one portion of the BOX layer and the second FDSOI transistors formed above the at least one portion of the BOX layer; and applying a single voltage across a backside of the Si substrate.

Abstract: Structures that include semiconductor fins and methods for forming a structure that includes semiconductor fins. A first fin comprised of n-type semiconductor material and a second fin comprised of p-type semiconductor material are formed.

Abstract: Structures that include semiconductor fins and methods for forming a structure that includes semiconductor fins. A first fin comprised of n-type semiconductor material and a second fin comprised of p-type semiconductor material are formed. A conductive strap is formed that couples an end of the first fin with an end of the second fin.

Abstract: Methods of locally changing the BOX layer of a MOSFET device to a high-k layer to provide different Vts with one backside voltage and the resulting device are provided. Embodiments include providing a Si substrate having a BOX layer formed over the substrate and a SOI layer formed over the BOX layer; implanting a high current of dopants into at least one portion of the BOX layer; performing a high-temperature anneal of the BOX layer; forming first and second fully depleted silicon-on-insulator (FDSOI) transistors on the SOI layer, the first FDSOI transistors formed above either the BOX layer or the at least one portion of the BOX layer and the second FDSOI transistors formed above the at least one portion of the BOX layer; and applying a single voltage across a backside of the Si substrate.

Abstract: Methods of locally changing the BOX layer of a MOSFET device to a high-k layer to provide different Vts with one backside voltage and the resulting device are provided. Embodiments include providing a Si substrate having a BOX layer formed over the substrate and a SOI layer formed over the BOX layer; implanting a high current of dopants into at least one portion of the BOX layer; performing a high-temperature anneal of the BOX layer; forming first and second fully depleted silicon-on-insulator (FDSOI) transistors on the SOI layer, the first FDSOI transistors formed above either the BOX layer or the at least one portion of the BOX layer and the second FDSOI transistors formed above the at least one portion of the BOX layer; and applying a single voltage across a backside of the Si substrate.

Abstract: Methods of locally changing the BOX layer of a MOSFET device to a high-k layer to provide different Vts with one backside voltage and the resulting device are provided. Embodiments include providing a Si substrate having a BOX layer formed over the substrate and a SOI layer formed over the BOX layer; implanting a high current of dopants into at least one portion of the BOX layer; performing a high-temperature anneal of the BOX layer; forming first and second fully depleted silicon-on-insulator (FDSOI) transistors on the SOI layer, the first FDSOI transistors formed above either the BOX layer or the at least one portion of the BOX layer and the second FDSOI transistors formed above the at least one portion of the BOX layer; and applying a single voltage across a backside of the Si substrate.