Abstract: A signal processing system includes a digital signal processing circuit, a power management unit, and a digital control circuit. The power management unit provides a first voltage to the digital signal processing circuit. When in a calibration mode the digital control circuit controls the power management unit to set the first voltage at a minimum preset value, controls the digital signal processing circuit to operate under a first calibration target frequency, triggers the digital signal processing circuit to perform a built-in self-test, raises the first voltage when the built-in self-test fails, triggers the digital signal processing circuit to perform the built-in self-test again, and stores the first calibration target frequency and a value of the first voltage corresponding to the first calibration target frequency to a non-volatile memory when the built-in self-test has succeeded.

Abstract: A phase-change material (PCM) switching device is provided. The PCM switching device includes: a base dielectric layer over a semiconductor substrate; a heater element embedded in the base dielectric layer, the heater element comprising a first metal element and configured to generate heat in response to a current flowing therethrough; a self-aligned dielectric layer disposed on the heater element, wherein the self-aligned dielectric layer comprises one of an oxide of the first metal element and a nitride of the first metal element, and the self-aligned dielectric layer is horizontally aligned with the heater element; a PCM region disposed on the self-aligned dielectric layer, wherein the PCM region comprises a PCM operable to switch between an amorphous state and a crystalline state in response to the heat generated by the heater element; and two metal pads electrically connected to the PCM region.

Abstract: A semiconductor structure includes a first inductor, a second inductor, and a first input/output (I/O) pad. The first I/O pad is coupled to the first inductor and the second inductor. The first I/O pad, a first central axis of a first magnetic field of the first inductor, and a second central axis of a second magnetic field of the second inductor are disposed sequentially along a first direction.

Abstract: Manufacturing flexibility and efficiency are obtained with a method, and resulting structure, in which RDL contact features can be formed and aligned to through silicon vias (TSV's) regardless of any potential mismatch in the respective critical dimensions (CD's) between the manufacturing process for forming the TSV's and the manufacturing process for forming the contact features. Various processes for a self-aligned exposure of the underlying TSV's, without the need for additional photolithography steps are provided.

Abstract: Phase change material (PCM) switches and methods of fabrication thereof that provide improved thermal confinement within a phase change material layer. A PCM switch may include a dielectric capping layer between a heater pad and the phase change material layer of the PCM switch that is laterally-confined such opposing sides of the dielectric capping layer the heater pad may form continuous surfaces extending transverse to the signal transmission pathway across the PCM switch. Heat transfer from the heater pad through the dielectric capping layer to the phase change material layer may be predominantly vertical, with minimal thermal dissipation along a lateral direction. The localized heating of the phase change material may improve the efficiency of the PCM switch enabling lower bias voltages, minimize the formation of regions of intermediate resistivity in the PCM switch, and improve the parasitic capacitance characteristics of the PCM switch.

Abstract: A semiconductor device is disclosed. The semiconductor device includes a semiconductor substrate, and a heater element on the semiconductor substrate, the heater element configured to generate heat in response to a current flowing therethrough. The semiconductor device also includes a conductor material having a programmable conductivity, and an insulator layer between the heater element and the conductor material, where the conductor material is configured to be programmed by applying one or more voltage differences to one or more of the heater element and the conductor material, and where a capacitance between the conductor material and the heater element is configured to be controlled by the voltage differences such that the capacitance is lower while the conductor material is being programmed than while the conductor material is not being programmed.

Abstract: A memory device is provided in various embodiments. The memory device, in those embodiments, has an ovonic threshold switching (OTS) selector comprising multiple layers of OTS materials to achieve a low leakage current and as well as relatively low threshold voltage for the OTS selector. The multiple layers can have at least one layer of low bandgap OTS material and at least one layer of high bandgap OTS material.

Abstract: Inductor device includes first and a second coils. First coil is wound into plural first circles. Second coil is wound into plural second circles. First connection member is coupled to first circle between outermost and innermost sides among first circles located at first area and first circle on outermost side among first circles located at second area. Second connection member is coupled to second circle on outermost side among second circles located at first area and second circle between outermost and innermost sides among second circles located at second area. At least two first circles of first circles are located at first area, and half of first circle of first circles is located at second area. Half of second circle of second circles is located at first area, and at least two second circles of second circles are located at second area.

Abstract: A cell array of a memory device includes: a first deck of memory cells arranged in a first row and a second row extending in a first horizontal direction and a plurality of columns extending in a second horizontal direction, wherein the memory cells in the second row in the first deck is displaced in the first horizontal direction with respect to the memory cells in the first row in the first deck; a first common word line metal track extending in the first horizontal direction, wherein both the memory cells in the first row and the memory cells in the second row are disposed on the first common word line metal track; and a plurality of first bit line metal tracks extending in the second horizontal direction, wherein each of the plurality of first bit line metal tracks is disposed on one of the first deck of memory cells.

Abstract: A method for fabricating a semiconductor device includes receiving a silicon substrate having an isolation feature disposed on the substrate and a well adjacent the isolation feature, wherein the well includes a first dopant. The method also includes etching a recess to remove a portion of the well and epitaxially growing a silicon layer (EPI layer) in the recess to form a channel, wherein the channel includes a second dopant. The method also includes forming a barrier layer between the well and the EPI layer, the barrier layer including at least one of either silicon carbon or silicon oxide. The barrier layer can be formed either before or after the channel. The method further includes forming a gate electrode disposed over the channel and forming a source and drain in the well.

Abstract: A one-time programmable (OTP) memory includes a plurality of bit lines, a plurality of word lines, and a plurality of memory cells, each memory cell of the plurality of memory cells including a first terminal coupled to a bit line of the plurality of bit lines, a second terminal coupled to a word line of the plurality of word lines, and a selector coupled between the first terminal and the second terminal and having a threshold voltage that is alterable by an electric current.

Abstract: Disclosed are methods and compositions for inducing proliferation in cardiomyocyte cells or for high-throughput assays.

Abstract: A system for processing data is provided. The system includes a data acquisition device and a central device. The data acquisition device is coupled to an object under test for receiving raw data from the object under test, and transmits the raw data. The central device receives the raw data from the data acquisition device, and performs a web application with a web interface for providing application data based on the raw data.

Abstract: A manufacturing method of a sample collection component, by which a removable light shielding component is disposed on a main body of the sample collection component to shield at least a portion of the light that passes through a storing space of the sample collection component.

Abstract: Some embodiments relate to an embedded memory device with vertically stacked source, drain and gate connections. The semiconductor memory device includes a substrate and a pillar of channel material extending in a first direction. A bit line is disposed over the pillar of channel material and is coupled to the pillar of channel material, and extends in a second direction that is perpendicular to the first direction. Word lines are on opposite sides of the pillar of channel material and extend in a third direction. The third direction is perpendicular to the second direction. A dielectric layer separates the word lines from the pillar of channel material. Source lines extend in the third direction over the substrate, directly beneath the word lines. Variable resistance memory layers are between the source lines and an outer sidewall of the dielectric layer, laterally surrounding the sidewalls of the pillar of channel material.

Abstract: The present application discloses an image capturing system and a method for adjusting focus. The image capturing system includes an image-sensing module, a plurality of processors, a display panel, and an audio acquisition module. A first processor is configured to detect objects in a preview image sensed by the image-sensing module and attach identification labels to the objects detected. The display panel shows the preview image along with the identification labels. The audio acquisition module converts an analog signal of a user's voice into digital voice data. One of the processors is configured to parse the digital voice data into user intent data. A second processor is configured to select a target from the detected objects in the preview image according to the user intent data and the identification labels of the detected objects, and control the image-sensing module to perform a focusing operation with respect to the target.

Abstract: A validation test piece is for validating a bio-sample detection device, which includes an insert port for insertion of the validation test piece and a detection module. The validation test piece includes a base seat, a test element, a standardized data and a top cover. The base seat includes a seat body and a receiving member disposed on the seat body. The test element is connected to the receiving member, and includes a test region to be detected by the detection module. The standardized data corresponds to a sample number of the test region. The top cover is connected to the base seat for covering the test element.

Abstract: An inductor device includes a first wire and a second wire. The first wire includes a first sub-wire and a second sub-wire. The first sub-wire is disposed in a first area. The second sub-wire is disposed in a second area, and the first sub-wire and the second sub-wire are located on different layers. The second wire includes a third sub-wire and a fourth sub-wire. The third sub-wire is disposed in the second area, and located below the second sub-wire. The fourth sub-wire is disposed in the first area, the third sub-wire and the fourth sub-wire are located on different layers, and the fourth sub-wire is located above the first sub-wire.

Abstract: A method for treating movement disorders is provided. The method includes the following operations. A central nervous signal of a patient with movement disorders is recorded. A first stimulation is delivered from a stimulator to the patient when an oscillation episode in a range of from about 3 Hz to about 20 Hz is observed in the central nervous signal. The first stimulation is adapted according to a measurable feature of the oscillation episode. The system for treating movement disorders is also provided.

Abstract: A memory device having a 3D structure provides MFMIS-FET memory cells with a high chip area density. The memory device includes a stack of memory cell layers interleaved with insulating layers. Channel vias penetrate through the stack. Channels of the memory cells are disposed in the channel vias. MFM portions of memory cells are sandwiched between the insulating layers in areas lateral to the channel vias. The MFM portions may be radially distributed from the channel vias and include a floating gate, a ferroelectric layer, and a gate electrode. The gate electrodes associated with a plurality of MFM structures may be united into a word line gate. The ferroelectric layer may wrap around the word line gate, whereby the ferroelectric layer is disposed above and below the word line gate as well as between the word line gate and each of the floating gates.