Abstract: A semiconductor device and method of manufacture are provided. In an embodiment a first semiconductor device and a second semiconductor device are formed within a semiconductor wafer and a scribe region between the first semiconductor device and the second semiconductor device is patterned. A singulation process is then utilized within the scribe region to singulate the first semiconductor device from the second semiconductor device. The first semiconductor device and the second semiconductor device are then bonded to a second semiconductor substrate and thinned in order to remove extension regions from the first semiconductor device and the second semiconductor device.

Abstract: A manufacturing method of a through substrate via includes at least the following steps. A protective liner is formed within an opening of a dielectric layer, where the opening exposes a portion of a semiconductor substrate underlying the dielectric layer. The portion of the semiconductor substrate is removed through the opening, where an overhang portion is formed at a top edge of the semiconductor substrate and masked by the protective liner after the removing. The overhang portion of the semiconductor substrate, the protective liner, and a portion of the dielectric layer adjoining the protective liner is removed to form a via hole. A conductive material is formed in the via hole.

Abstract: An inductor device includes a first coil and a second coil. The first coil is wound into a plurality of first circles, and the second coil is wound into a plurality of second circles. At least two of the second circles are interlaced with at least two of the first circles on a first side. The at least two of the second circles are disposed adjacent to each other on the first side. At least one of the first circles is only interlaced with at least one of the second circles on a second side. At least another one of the first circles is only interlaced with at least another one of the second circles on the second side.

Abstract: Disclosed are systems and methods for expanding eyebox for a viewer, including (but not limited to) for the near eye display applying retinal projecting technologies from a head wearable device such as smart glasses. This disclosure includes two embodiments. The first embodiment applying a principle of “light-split” comprises an optical duplicator to generate multiple instances of an incident light signal to achieve eyebox expansion for a viewer. The second embodiment applying a principle of “time-split” comprises an optical reflector moving to redirect multiple light signals at a different angle of incidence to achieve eyebox expansion for a viewer.

Abstract: A network device receives, from multiple smart cameras located at different road segments of multiple real-world road segments, first data describing a location and configuration of each of the multiple real-world road segments, and second data describing movement of one or more objects at each of the multiple real-world road segments. The network device generates multiple virtual road segments based on the first data, wherein each of the multiple virtual road segments describes one of the multiple real-world road segments; and uses a physics engine to simulate, based on the generated multiple virtual road segments and the second data, movement of vehicles or pedestrians through the multiple real-world road segments to analyze traffic characteristics, trends or events. The network device generates road segment alterations for reconfiguring one or more of the multiple real-world road segments based on the analysis of the traffic characteristics, trends, or events.

Abstract: The present application discloses an image capturing system and a method for adjusting focus. The image capturing system includes a first image-sensing module, a plurality of processors, a display panel, and a second image-sensing module. A first processor detects objects in the preview image sensed by the first image-sensing module and attach labels to the detected objects. The display panel displays the preview image with the labels of the objects detected. The second image-sensing module acquires user’s gaze data. A second processor selects a target in the preview image according to a gazed region on the display panel that the user is looking at, and controls the first image-sensing module to focus on the target. The first processor, the second processor, and/or a third processor detect the gazed region according to the user’s gaze data.

Abstract: A semiconductor device includes a semiconductor substrate, a first semiconductor layer, a first floating gate electrode, a first control gate electrode, an erase gate electrode, and a blocking layer. The semiconductor substrate has a first source/drain region. The first semiconductor layer extends upward from the first source/drain region of the semiconductor substrate. The first floating gate electrode surrounds the first semiconductor layer. The first control gate electrode surrounds the first floating gate electrode and the first semiconductor layer. The erase gate electrode is over the first floating gate electrode and the first control gate electrode. The erase gate electrode surrounds the first semiconductor layer. The blocking layer has a first portion between the first floating gate electrode and the first control gate electrode and a second portion between the erase gate electrode and the first semiconductor layer.

Abstract: A memory cell, an integrated circuit and method of manufacturing the same are provided. The memory device includes a substrate, gate layers and insulating layers, an isolation column, a channel layer, a first conductive feature, a second conductive feature, a storage layer and a pair of isolation structures. The isolation column extends through the gate layers and the insulating layers along a first direction. The channel layer laterally covers the isolation column. The first conductive feature and second conductive feature extend along the first direction and adjacent to the isolation column. The storage layer is disposed between the gate layers and the channel layer. The pair of isolation structures extends along the first direction. The pair of isolation structures includes a first isolation structure disposed between the first conductive feature and the gate layers, and a second isolation structure disposed between the second conductive feature and the gate layers.

Abstract: A manufacturing method of a semiconductor structure includes at least the following steps. A patterned mask layer with a first opening is formed on a dielectric layer overlying a semiconductor substrate. A portion of the dielectric layer accessibly exposed by the first opening of the patterned mask layer is removed to form a second opening. A first protective film is formed on inner sidewalls of the dielectric layer and the patterned mask layer, where the second opening and the first protective film are formed at the same step. A second protective film is formed on the first protective film to form a protective structure covering the inner sidewalls. A portion of the semiconductor substrate accessibly exposed by the second opening is removed to form a via hole including an undercut underlying the protective structure. The via hole is trimmed and a through substrate via is formed in the via hole.

Abstract: A manufacturing method of a semiconductor structure includes at least the following steps. A patterned mask layer with a first opening is formed on a dielectric layer overlying a semiconductor substrate. A portion of the dielectric layer accessibly exposed by the first opening of the patterned mask layer is removed to form a second opening. A first protective film is formed on inner sidewalls of the dielectric layer and the patterned mask layer, where the second opening and the first protective film are formed at the same step. A second protective film is formed on the first protective film to form a protective structure covering the inner sidewalls. A portion of the semiconductor substrate accessibly exposed by the second opening is removed to form a via hole including an undercut underlying the protective structure. The via hole is trimmed and a through substrate via is formed in the via hole.

Abstract: An anti-fuse memory cell includes a substrate, a gate dielectric layer over the substrate, a word line gate over the gate dielectric layer, a first implant region on a first side of the word line gate, a bit line contact plug over the first implant region, a second implant region on a second side of the word line gate opposite the first side of the word line gate, an oxidized region on the second implant region and having a convex upper surface and a source line gate over the convex upper surface of the oxidized region.

Abstract: An audio codec circuit includes a voltage detecting circuit, an output processing circuit, a digital-to-analog conversion circuit, and an audio amplifying circuit. The voltage detecting circuit is configured to detect an input voltage of an input power. The output processing circuit obtains a first output compensation value according to the input voltage, an output circuit parameter, and a first output spec. The output processing circuit processes a digital audio and compensates the processed audio by the first output compensation value. The digital-to-analog conversion circuit is configured to perform digital-to-analog conversion on the compensated audio to obtain an analog audio. The audio amplifying circuit is configured to amplify the analog audio and output the amplified audio.

Abstract: A method for fabricating a semiconductor device is provided. The method includes depositing a first dielectric layer over a substrate; depositing a sacrificial layer over the first dielectric layer; depositing a second dielectric layer over the sacrificial layer; depositing an erase gate electrode layer over the second dielectric layer; etching a memory hole in the erase gate electrode layer, the sacrificial layer, and the first and second dielectric layers; and forming a semiconductor layer in the memory hole.

Abstract: A state detection device in an audio interface includes: a first voltage detection circuit, a second voltage detection circuit and a state determination circuit. The first voltage detection circuit is coupled to a first contact and a second contact of an audio jack socket, for detecting a voltage across the first contact and the second contact to generate a first detection value. The second voltage detection circuit is coupled to a third contact of the audio jack socket, for detecting a voltage on the third contact to generate a second detection value. The state determination circuit is coupled to the first voltage detection circuit and the second voltage detection circuit, for determining a water ingress state of the audio jack socket according to the first detection value, and a connector type of an audio plug that is inserted into the audio jack socket according to the second detection value.

Abstract: A state detection device in an audio interface includes: a first voltage detection circuit, a second voltage detection circuit and a state determination circuit. The first voltage detection circuit is coupled to a first contact and a second contact of an audio jack socket, for detecting a voltage across the first contact and the second contact to generate a first detection value. The second voltage detection circuit is coupled to a third contact of the audio jack socket, for detecting a voltage on the third contact to generate a second detection value. The state determination circuit is coupled to the first voltage detection circuit and the second voltage detection circuit, for determining a water ingress state of the audio jack socket according to the first detection value, and a connector type of an audio plug that is inserted into the audio jack socket according to the second detection value.

Abstract: An electronic device is provided. The electronic device includes: a display panel, a display controller, and a host. The display controller is configured to control displaying of the display panel. The host is electrically connected to the display controller. The host executes an application to render a display image, and transmits the display image to the display controller through an image-transmission channel between the host and the display controller. The display controller detects whether pixels in a specific area of the display image satisfy a predetermined condition. In response to the pixels in the specific area satisfying the predetermined condition, the display controller triggers a virtual input signal, and transmits the virtual input signal to the host through a data-transmission channel between the host and the display controller, so that the host executes a specific operation corresponding to the virtual input signal.

Abstract: A method for treating neural disorders is provided. The method includes the following operation. A stimulation is delivered to a layer of a cortex of a patient with a neural disorder, wherein the stimulation is delivered to less than all layers of the cortex of the patient. In another method for treating neural disorders, a stimulation is delivered to a cortex of a patient with a neural disorder, wherein the stimulation delivered to one of a plurality of layers of the cortex is stronger than to other layers of the cortex. The system for treating neural disorder is also provided. The system includes a stimulation signal generator and a layer-specific stimulation means. The layer-specific stimulation means is coupled to the stimulation signal generator, configured to deliver a stimulation to a specific layer of a cortex of a patient with a neural disorder.

Abstract: An integrated circuit is provided. The integrated circuit includes a first trace, a second trace and a third trace. The first trace, the second trace and the third trace are each a continuous trace. The first trace, the second trace and the third trace together use only two conductor layers of a semiconductor structure. In a crossing area of the first trace, the second trace and the third trace, the first trace crosses the second trace once, the first trace crosses the third trace once, and the second trace crosses the third trace once.

Abstract: A device is disclosed herein. The device includes at least two transmit portions and at least one contact portion. Each of the at least two transmit portions is configured to receive a bit line signal. The at least one contact portion is couple to the at least two transmit portions respectively and configured to transmit the bit line signals from the least two transmit portions to a source line.

Abstract: An inductor and an integrated circuit are provided. The inductor includes a first coil, a second coil, and a third coil. The first coil has a first input terminal and a first output terminal, and the first coil is winded in a first direction from the first input terminal to the first output terminal. The second has a second input terminal and a second output terminal, and the second coil is winded in a second direction which is opposite to the first direction from the second input terminal to the second output terminal. The third has a third input terminal and a third output terminal, and the third input terminal is connected to the first input terminal and the second input terminal.