Abstract: The present disclosure provides a method for treating liver cirrhosis by using a composition including mesenchymal stem cells, extracellular vesicles produced by the mesenchymal stem cells, and growth factors. The composition of the present disclosure achieves the effect of treating liver cirrhosis through various efficacy experiments.

Abstract: The present invention provides a latching guide structure arranged inside a door of semiconductor carrier. The latching guide structure comprises an upper latching part, a lower latching part, at least one elastic unit and a driver. Moreover, a first guiding portion of the upper latching part is matched with a second guiding portion of the lower latching part, therefore to define the installation space for the at least one elastic unit. On the other hand, the driver simultaneously actuates an upper actuating unit of the first guiding portion and a lower actuating unit of the second guiding portion to linearly move in reverse direction therebetween. The range of the linear motion of the upper actuating unit and the lower actuating unit represents the compression or extension of the at least one elastic unit, determining to control the open/close status of the upper latching part and the lower latching part.

Abstract: The present invention provides a latching guide structure arranged inside a door of semiconductor carrier. The latching guide structure comprises an upper latching part, a lower latching part, at least one elastic unit and a driver. Moreover, a first guiding portion of the upper latching part is matched with a second guiding portion of the lower latching part, therefore to define the installation space for the at least one elastic unit. On the other hand, the driver simultaneously actuates an upper actuating unit of the first guiding portion and a lower actuating unit of the second guiding portion to linearly move in reverse direction therebetween. The range of the linear motion of the upper actuating unit and the lower actuating unit represents the compression or extension of the at least one elastic unit, determining to control the open/close status of the upper latching part and the lower latching part.

Abstract: A compound of formula (I), wherein R1R2R3 are defined in the disclosure. The compound of formula (I) is used as a catalyst for lactide polymerization to reduce the temperature and the time of the polymerization reaction, thereby producing polylactic acid (PLA) having high molecular weight. The present invention also provides a method of preparing the compound of formula (1) and a method of synthesizing polylactic acid that is catalyzed by the compound of formula (1).

Abstract: A semiconductor device includes a source/drain feature over a semiconductor substrate, channel layers over the semiconductor substrate and connected to the source/drain feature, a gate portion between vertically adjacent channel layers, and an inner spacer between the source/drain feature and the gate portion and between adjacent channel layers. The semiconductor device further includes an air gap between the inner spacer and the source/drain feature.

Abstract: A chip package includes a carrier board, a chip, a light transmissive sheet, a supporting element, and a molding material. The chip is located on the carrier board and has a sensing area. The light transmissive sheet is located above the supporting element and covers the sensing area of the chip. The supporting element is located between the light transmissive sheet and the chip, and surrounds the sensing area of the chip. The molding material is located on the carrier board and surrounds the chip and the light transmissive sheet. A top surface of the molding material is lower than a top surface of the light transmissive sheet.

Abstract: A chip package includes a light transmissive sheet, a chip, a bonding layer, and an insulating layer. The light transmissive sheet has a protruding portion. A first surface of the chip faces toward the light transmissive sheet and has a sensing area. The bonding layer is located between the chip and the light transmissive sheet. The sum of a thickness of the chip and a thickness of the bonding layer is greater than or equal to a thickness of the light transmissive sheet. A protruding portion of the light transmissive sheet protrudes from a sidewall of the chip and a sidewall of the bonding layer. The insulating layer extends from a second surface of the chip to the protruding portion of the light transmissive sheet along the sidewall of the chip and the sidewall of the bonding layer.

Abstract: A heat dissipation module for dissipating heat from a heat source of a projection apparatus includes a thermoelectric module, a heat dissipation member, an absorption material, a transmission member and an insulating material. The thermoelectric module is disposed between the heat source and the heat dissipation member and has a cold side and a hot side opposite to each other, where the cold side is for dissipating heat from the heat source, and the hot side contacts with the heat dissipation member. The transmission member has a connection end and an evaporation end, wherein the connection end connects with the absorption material. The insulating material covers the absorption material and the transmission member. A projection apparatus uses the heat dissipation module. The heat dissipation module and the projection apparatus can prevent possibility of condensed moisture flowing into the system to damage electronic devices, and therefore have higher structural reliability.

Abstract: A manufacturing method of a chip package includes forming a temporary bonding layer on a carrier; forming an encapsulation layer on a top surface of a wafer or on the temporary bonding layer; bonding the carrier to the wafer, in which the encapsulation layer covers a sensor and a conductive pad of the wafer; patterning a bottom surface of the wafer to form a through hole, in which the conductive pad is exposed through the through hole; forming an isolation layer on the bottom surface of the wafer and a sidewall of the through hole; forming a redistribution layer on the isolation layer and the conductive pad that is in the through hole; forming a passivation layer on the isolation layer and the redistribution layer; and removing the temporary bonding layer and the carrier.

Abstract: A chip package includes a semiconductor substrate, a supporting element, an antenna layer, and a redistribution layer. The semiconductor substrate has an inclined sidewall and a conductive pad that protrudes from the inclined sidewall. The supporting element is located on the semiconductor substrate, and has a top surface facing away from the semiconductor substrate, and has an inclined sidewall adjoining the top surface. The antenna layer is located on the top surface of the supporting element. The redistribution layer is located on the inclined sidewall of the supporting element, and is in contact with a sidewall of the conductive pad and an end of the antenna.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate having a first surface and a second surface opposite thereto. A gallium nitride (GaN)-based device layer is formed on the first surface of the semiconductor substrate and has source, drain, and gate contact regions. First, second, and third through-substrate vias (TSVs) pass through the semiconductor substrate and are respectively electrically connected to the source, drain, and gate contact regions. An insulating liner layer is formed on the second surface of the semiconductor substrate and extends into the semiconductor substrate to separate the second and third TSVs from the semiconductor substrate. A semiconductor package assembly including the semiconductor device structure is also provided.

Abstract: A chip package includes a chip and a conductive structure. A first surface of the chip has a photodiode. A second surface of the chip facing away from the first surface has a recess aligned with the photodiode. The conductive structure is located on the first surface of the chip.

Abstract: An uninterruptible power system (UPS) testing method includes the steps of setting an operational decline table, setting an initial value, collecting data, inputting targets, executing multi-algorithm, and indicating a warning or an approval. Wherein, battery cells of the UPS are repeatedly tested when being actually used at different temperatures to set the operational decline table and the initial time value; and data about temperatures and time periods of the battery in operation are continuously collected for a user to execute algorithms based on designated conditions to predict the battery state in a future time period; and an indication message is generated for the user to determine whether the battery is still usable or has to be replaced. In this manner, it is able to estimate the running time of a target time of the UPS without the need of performing an actual electrical discharge procedure.

Abstract: A chip package includes a high voltage withstanding substrate and a device chip. The high voltage withstanding substrate has a main body, a functional layer, and a grounding layer. The main body has a top surface, a bottom surface opposite the top surface, a through hole through the top surface and the bottom surface, and a sidewall surrounding the through hole. The functional layer is located on the top surface. The grounding layer covers the bottom surface and the sidewall. The device chip is located on the functional layer, and has a grounding pad that faces the main body. The grounding pad is electrically connected to the grounding layer in the through hole.

Abstract: A method for manufacturing a composite electrolyte includes steps as follows. A eutectic mixture is provided. The eutectic mixture includes a lithium salt and a hydrogen-bond donor. The lithium salt includes a hydrogen-bond acceptor. A polymer material is provided. The polymer material includes a polymer. A mixing step is conducted. The eutectic mixture and the polymer material are mixed and heated to form an electrolyte precursor. A molding step is conducted. The electrolyte precursor is cooled to obtain the composite electrolyte.

Abstract: A chip package includes a chip, a sidewall structure that has a first light-shielding layer, a second light-shielding layer, and a cover. The chip has a light emitter and a light receiver that are located on a top surface of the chip. The sidewall structure is located on the top surface of the chip and has two aperture areas. The light emitter and the light receiver are respectively located in the two aperture areas. The sidewall structure surrounds the light emitter and the light receiver, and at least one surface of the sidewall structure has the first light-shielding layer. The second light-shielding layer is located between the chip and the sidewall structure. The cover is located on a surface of the sidewall structure facing away from the chip, and at least covers the light receiver and the sidewall structure that surrounds the light receiver.

Abstract: A chip package includes a chip and a conductive structure. A first surface of the chip has a photodiode. A second surface of the chip facing away from the first surface has a recess aligned with the photodiode. The conductive structure is located on the first surface of the chip.

Abstract: A chip package includes a semiconductor substrate, a supporting element, an antenna layer, and a redistribution layer. The semiconductor substrate has an inclined sidewall and a conductive pad that protrudes from the inclined sidewall. The supporting element is located on the semiconductor substrate, and has a top surface facing away from the semiconductor substrate, and has an inclined sidewall adjoining the top surface. The antenna layer is located on the top surface of the supporting element. The redistribution layer is located on the inclined sidewall of the supporting element, and is in contact with a sidewall of the conductive pad and an end of the antenna.

Abstract: A manufacturing method of a chip package includes forming a temporary bonding layer on a carrier; forming an encapsulation layer on a top surface of a wafer or on the temporary bonding layer; bonding the carrier to the wafer, in which the encapsulation layer covers a sensor and a conductive pad of the wafer; patterning a bottom surface of the wafer to form a through hole, in which the conductive pad is exposed through the through hole; forming an isolation layer on the bottom surface of the wafer and a sidewall of the through hole; forming a redistribution layer on the isolation layer and the conductive pad that is in the through hole; forming a passivation layer on the isolation layer and the redistribution layer; and removing the temporary bonding layer and the carrier.

Abstract: The present invention provides an anode material of nano-silicon. The anode material has multilayer-graphene as a carrier and is coated with silicon suboxide and with an amorphous carbon layer. The anode material has multilayer-graphene to serve as a carrier, nano-silicon which is adsorbed on the multilayer-graphene and both the multilayer-graphene and the nano-silicon serve as a core, silicon suboxide and the amorphous carbon layer to cover the multilayer-graphene and the nano-silicon, and a plurality of buffering holes which are disposed on the anode material to provide buffering space. An anode material of high quality is realized by coating multilayer-graphene which serves as a carrier of nano-silicon with silicon suboxide and with the amorphous carbon layer.