Abstract: A curved display and a method for binding a cover glass of the curved display are provided. The curved display includes a display module, a frame body and a cover glass. The frame body has a first flat surface and a second flat surface opposite to the first flat surface, in which the first flat surface is adhered to the display module. The cover glass has a binding flat surface and an application surface opposite to the binding flat surface, in which the binding flat surface is adhered to the second flat surface of the frame body, and the application surface is a surface with curvature. The second flat surface of the frame body is set with a first alignment mark, and the binding flat surface of the cover glass is set with a second alignment mark, and the first alignment mark corresponds to the second alignment mark.

Abstract: A scan test device includes a scan flip flop circuit and a clock gating circuit. The scan flip flop circuit is configured to receive a scan input signal according to a scan clock signal, and to output the received scan input signal to be a test signal. The clock gating circuit is configured to selectively mask the scan clock signal according to a predetermined bit of the test signal and a scan enable signal, in order to generate a test scan clock signal for testing at least one core circuit.

Abstract: An electronic device test database generating method, comprising: (a) acquiring cell layout information of a target electronic device; (b) generating possible defect location information of the target electronic device according to the cell layout information, wherein the possible defect location information comprises at least one possible defect location of the target electronic device; (c) testing the target electronic device according to the possible defect location information to generate a testing result; and (d) generating an electronic device test database according to the testing result.

Abstract: A wafer testing machine and a method for training an artificial intelligence (AI) model to test wafers are provided. The wafer contains multiple dies. The method includes the following steps of: determining a target die from the dies; selecting multiple reference dies close to the target die based on the target die and a preset range; generating a main training data which includes a measured value of the target die and the measured value of each reference die; generating an auxiliary training data which indicates whether each reference die is a passed die or a failed die; and training the AI model using the main training data and the auxiliary training data.

Abstract: An improved insulation protection structure comprises a sensor film, a chip outline, a protective film, and an insulating cement layer. The chip outline is on the sensor film, the protective film is on the chip outline, the insulating cement layer is between the chip outline and the protective film. The insulating cement layer comprises at least one surface facing inward the chip outline, retracted toward the direction of the chip outline and forms a retracted region along at least one side of the sensor film. Area of the proposed retracted region is preferably no more than 20% of that of the total insulating cement layer, and the conventional issues such as sulphide corrosion are solved. The proposed insulating cement layer can be cured merely at room temperature, and widely used for adhesive materials including both a gel and film, thus characterized by wider application range and better industrial applicability.

Abstract: The present disclosure relates to a circuit testing system, including a control circuit and an I/O interface circuit. The control circuit is electrically connected to a test machine, and is configured to receive a scan control signal. The I/O interface circuit is electrically connected to the control circuit, the test machine, the scan chain circuit and a circuit under test. When the scan control signal is at a first level, the control circuit is configured to control the I/O interface circuit to propagate a scan test signal sended from the test machine to the scan chain circuit. When the scan control signal is at a second level, the control circuit is configured to control the I/O interface circuit to propagate a response signal generated by the circuit under test to the test machine.

Abstract: A circuit having multiple scan modes is disclosed. The circuit includes a first circuit block and a second circuit block. The first circuit block corresponds to a first scan mode of the multiple scan modes, and the first circuit block includes at least one first scan chain for receiving a test signal from an external automatic test equipment. The second circuit block corresponds to a second scan mode of the multiple scan modes, and the second circuit block includes at least one second scan chain for receiving another test signal from the external automatic test equipment. The second scan chain includes at least one specific flip-flop positioned in the first circuit block, and the specific flip-flop is configured to drive the second circuit block.

Abstract: The present disclosure relates to a circuit testing system, including a control circuit and an interface circuit. The control circuit is electrically connected to a test machine, and configured to receive a scan control signal. The I/O interface circuit is electrically connected to the control circuit, the test machine, the scan chain circuit and a circuit under test. When the scan control signal is at a first level, the control circuit is configured to control the I/O interface circuit to conduct the scan chain circuit to the test machine. When the scan control signal is at a second level, the control circuit is configured to control the I/O interface circuit to conduct the circuit under test to the test machine so as to propagate a response signal generated by the circuit under test to the test machine.

Abstract: A test pattern generating method for generating a test pattern for a circuit under test. The test pattern generating method comprises: (a) computing a plurality of signal delay values which a plurality of cells have due to different defects; (b) comparing the signal delay values and signal path delay information of a target circuit to generate a fault model; and (c) generate at least one test pattern according to the fault model.

Abstract: A curved display and a method for binding a cover glass of the curved display are provided. The curved display includes a display module, a frame body and a cover glass. The frame body has a first flat surface and a second flat surface opposite to the first flat surface, in which the first flat surface is adhered to the display module. The cover glass has a binding flat surface and an application surface opposite to the binding flat surface, in which the binding flat surface is adhered to the second flat surface of the frame body, and the application surface is a surface with curvature. The second flat surface of the frame body is set with a first alignment mark, and the binding flat surface of the cover glass is set with a second alignment mark, and the first alignment mark corresponds to the second alignment mark.

Abstract: An improved insulation protection structure comprises a sensor film, a chip outline, a protective film, and an insulating cement layer. The chip outline is on the sensor film, the protective film is on the chip outline, the insulating cement layer is between the chip outline and the protective film. The insulating cement layer comprises at least one surface facing inward the chip outline, retracted toward the direction of the chip outline and forms a retracted region along at least one side of the sensor film. Area of the proposed retracted region is preferably no more than 20% of that of the total insulating cement layer, and the conventional issues such as sulphide corrosion are solved. The proposed insulating cement layer can be cured merely at room temperature, and widely used for adhesive materials including both a gel and film, thus characterized by wider application range and better industrial applicability.

Abstract: An SRAM structure includes a substrate. A first active region, a second active region, a third active region and a fourth active region are disposed on the substrate. A first gate structure includes a first part, a second part and a third part disposed on the substrate. The first part and the third part are perpendicular to the first active region. The second part is parallel to the first active region. The first part covers the first active region, the second active region and the fourth active region. The third part covers the fourth active region. The second part is disposed on an insulating region between the second active region and the fourth active region, and the second part contacts the first part and the third part.

Abstract: A touch panel includes a touch sensing layer, a flexible circuit board and an anisotropic conductive film. The touch sensing layer includes sensing pads and a reserved room, and the reserved room is arranged outside the sensing pads. The flexible circuit board includes conductive pads, the outermost conductive pad is provided with a virtual pattern, and the position of the virtual pattern corresponds to the position of the reserved room. The anisotropic conductive film is arranged between the touch sensing layer and the flexible circuit board, and the sensing pads are respectively electrically connected to the conductive pads through the anisotropic conductive film.

Abstract: A touch panel includes a touch sensing layer, a flexible circuit board and an anisotropic conductive film. The touch sensing layer includes sensing pads and a reserved room, and the reserved room is arranged outside the sensing pads. The flexible circuit board includes conductive pads, the outermost conductive pad is provided with a virtual pattern, and the position of the virtual pattern corresponds to the position of the reserved room. The anisotropic conductive film is arranged between the touch sensing layer and the flexible circuit board, and the sensing pads are respectively electrically connected to the conductive pads through the anisotropic conductive film.

Abstract: A microfluidic chip includes a chip main body having a rotation center, a sample reservoir, a liquid groove, multiple reaction chambers, a first inlet channel and multiple second inlet channels, and a sealing membrane connected to the chip main body. The liquid groove has a feeding groove portion extending around the rotation center and the sample reservoir, and multiple metering groove portions extending away from the rotation center. The first inlet channel communicates the sample reservoir and the feeding groove portion. Each second inlet channel communicates a respective metering groove portion and a respective reaction chamber. The depth of the first inlet channel is smaller than those of the sample reservoir and the feeding groove portion. The depth of each second inlet channel is smaller than those of the respective metering groove portion, the respective reaction chamber and the first inlet channel.

Abstract: An SRAM structure includes a substrate. A first active region, a second active region, a third active region and a fourth active region are disposed on the substrate. A first gate structure includes a first part, a second part and a third part disposed on the substrate. The first part and the third part are perpendicular to the first active region. The second part is parallel to the first active region. The first part covers the first active region, the second active region and the fourth active region. The third part covers the fourth active region. The second part is disposed on an insulating region between the second active region and the fourth active region, and the second part contacts the first part and the third part.

Abstract: The present disclosure relates to a circuit testing system, including a control circuit and an interface circuit. The control circuit is electrically connected to a test machine, and configured to receive a scan control signal. The I/O interface circuit is electrically connected to the control circuit, the test machine, the scan chain circuit and a circuit under test. When the scan control signal is at a first level, the control circuit is configured to control the I/O interface circuit to conduct the scan chain circuit to the test machine. When the scan control signal is at a second level, the control circuit is configured to control the I/O interface circuit to conduct the circuit under test to the test machine so as to propagate a response signal generated by the circuit under test to the test machine.

Abstract: The present disclosure relates to a circuit testing system, including a control circuit and an I/O interface circuit. The control circuit is electrically connected to a test machine, and is configured to receive a scan control signal. The I/O interface circuit is electrically connected to the control circuit, the test machine, the scan chain circuit and a circuit under test. When the scan control signal is at a first level, the control circuit is configured to control the I/O interface circuit to propagate a scan test signal sended from the test machine to the scan chain circuit. When the scan control signal is at a second level, the control circuit is configured to control the I/O interface circuit to propagate a response signal generated by the circuit under test to the test machine.

Abstract: A system for predicting types of pathogens in patients with septicemia is provided. The system includes at least one sensor and a processor. The sensor is used to sense current physiological data including at least one of body temperature, blood pressure, and pulse. The processor is configured to calculate at least one feature value according to the current physiological data, and input the feature value into a machine learning model to determine one of categories including at least two of uninfected, fungal infected, contaminated bacteria infected, Gram-negative infected, and Gram-positive infected.

Abstract: A system for enhancing accuracy of body surface temperature measurement includes: a core body temperature sensor configured to obtain a core body temperature data of a user, a heart rate sensor configured to obtain a heart rate data of the user, a physical indicator sensor configured to obtain at least one physical indicator of the user, a body surface temperature sensor configured to obtain a body surface temperature data of the user, an environment temperature sensor configured to obtain an environment temperature data, a humidity sensor configured to obtain an environment humidity data, and a processor. The processor is configured to calculate a representative feature temperature data of the user according to the core temperature data, the heart rate data, the at least one physical indicator, the body surface temperature data, the environment temperature data, and the environment humidity data.