Abstract: A metal mesh structure capable of reducing breakpoint short circuits, including a plurality of first main channel wires, a plurality of second main channel wires, a plurality of first virtual wires and a plurality of second virtual wires. The first main channel wires are spaced apart and aligned in a first direction. The second main channel wires are spaced apart and aligned in a second direction. The second main channel wires cross the first main channel wires to form a plurality of main channel meshes. A method of manufacturing a metal mesh structure capable of reducing breakpoint short circuits is further provided. Given the aforesaid structure and method, the metal mesh is effective in reducing breakpoint short circuits.

Abstract: A TFT array manufacturing method is disclosed herein and includes steps: forming a first metal layer on a substrate; depositing a first insulating layer to cover the first metal layer; forming an oxide semiconductor layer on the first insulating layer in a TFT area; forming a second insulating layer on the first insulating layer and the oxide semiconductor layer; etching the second insulating layer in the TFT area to expose the oxide semiconductor layer and etching the second insulating layer and the first insulating layer in a signal wire area simultaneously to expose the first metal layer; and forming a second metal layer on the second insulating layer of the TFT area, and the second metal layer being connected the oxide semiconductor layer, and forming the second metal layer on the first metal layer of the signal wire area to contact the first metal, layer.

Abstract: A TFT array manufacturing method is disclosed herein and includes steps: forming a first metal layer on a substrate; depositing a first insulating layer to cover the first metal layer; forming an oxide semiconductor layer on the first insulating layer in a TFT area; forming a second insulating layer on the first insulating layer and the oxide semiconductor layer; etching the second insulating layer in the TFT area to expose the oxide semiconductor layer and etching the second insulating layer and the first insulating layer in a signal wire area simultaneously to expose the first metal layer; and forming a second metal layer on the second insulating layer of the TFT area, and the second metal layer being connected the oxide semiconductor layer, and forming the second metal layer on the first metal layer of the signal wire area to contact the first metal, layer.

Abstract: The present invention discloses a manufacturing method for a switch and an array substrate. The method comprises: firstly, forming sequentially a first metal layer, an insulating layer, a semiconductor layer, an ohmic contact layer, a second metal layer, a third metal layer and a photoresist layer on a base substrate; after patterning the photoresist layer, etching the third metal layer and the second metal layer to form the input electrode and the output electrode of the switch; using a stripper comprising at least 30% by weight of amine in order to remove the photoresist layer and the residual second metal layer; and finally, etching the ohmic contact layer. Through the above steps, the present invention can avoid the electrical abnormality of the switch and increase process yield of the array substrate.

Abstract: The present invention provides a thin film transistor comprising at least a gate electrode formed on a substrate, and a gate insulating layer in contacting the gate electrode, and an oxide semiconductor layer deposited on the other side of the gate insulating layer. The concentration of hydrogen in the gate insulating layer has a gradient distribution, wherein the concentration of hydrogen adjacent the gate electrode is higher; and while the concentration of hydrogen adjacent the oxide semiconductor layer is lower. The present invention further provides a method for manufacturing a thin film transistor and an according thin-film-transistor liquid crystal display device.

Abstract: A display panel, a transistor and the manufacturing method thereof are disclosed. The manufacturing method includes: forming a first electrode, a first insulation layer, a sacrificial layer, and a second/third electrode metal layer on a substrate in turn; etching the second/third electrode metal layer to expose at least portions of the sacrificial layer; and dry-etching the at least portions of the exposed sacrificial layer to expose at least portions of the first insulation layer. The etching selectivity ratio of the sacrificial layer to the first insulation layer is larger than a first value when the conditions of the etching process are the same. The first value is larger than one, in this way, the stability and the electron mobility of the transistor are enhanced.

Abstract: The present invention discloses a transistor, the preparation method thereof, and a display panel. The transistor comprises: a gate electrode; a gate insulating layer covering the gate electrode; an oxide semiconductor layer formed on the gate insulating layer; a first protective layer formed on the oxide semiconductor layer; a source/drain electrode connected with the oxide semiconductor layer; and a second protective layer covering the source/drain electrode; wherein, the hydrogen atom content per unit volume of the first protective layer is less than that of the gate insulating layer, and the hydrogen atom content per unit volume of the gate insulating layer is less than that of the second protective layer. Through the above solutions, the present invention can suppress the combination of the oxygen atom of the semiconductor layer in the transistor and the external hydrogen atom, to improve the performance and stability of the device.

Abstract: A thin-film transistor (TFT) includes a gate electrode, a gate dielectric layer, a semiconductor layer, source/drain electrodes, a passivation layer and a protection layer. The gate electrode is disposed on a substrate. The gate dielectric layer covers the gate electrode and the substrate. The semiconductor layer is disposed on the gate dielectric layer and above the gate electrode. The semiconductor layer has a channel region disposed above the gate electrode and source/drain regions disposed at both sides of the channel region. The source/drain electrodes are disposed on the source/drain regions of the semiconductor layer and each has a barrier layer disposed on the source/drain regions of the semiconductor layer and a conductive layer disposed on the barrier layer. The passivation layer is disposed over the surface of the source/drain electrodes. The protection layer is disposed over the substrate, the passivation layer, and the channel region of the semiconductor layer.

Abstract: The present invention discloses a manufacturing method for a switch and an array substrate. The method comprises: firstly, forming sequentially a first metal layer, an insulating layer, a semiconductor layer, an ohmic contact layer, a second metal layer, a third metal layer and a photoresist layer on a base substrate; after patterning the photoresist layer, etching the third metal layer and the second metal layer to form the input electrode and the output electrode of the switch; using a stripper comprising at least 30% by weight of amine in order to remove the photoresist layer and the residual second metal layer; and finally, etching the ohmic contact layer. Through the above steps, the present invention can avoid the electrical abnormality of the switch and increase process yield of the array substrate.

Abstract: The present invention discloses a thin film transistor and an active matrix flat display device, the thin film transistor comprising a gate electrode, a first insulating layer, a source electrode, a drain, and multiple oxide semiconductor layers, wherein, the multiple oxide semiconductor layers sequentially laminate between the source electrode, the drain electrode and the first insulating layer and comprise a first oxide semiconductor layer disposed close to the first layer and a second oxide semiconductor layer electrically connected with the source electrode and the drain electrode, and the resistivity of the first oxide semiconductor layer greater than 104 ?·cm, the resistivity of the second oxide semiconductor layer smaller than 1 ?·cm. Therefore, it ensures normal operation of the thin film transistor in order to ensure the display quality of the active matrix flat panel display device.

Abstract: The present invention discloses an active-matrix panel display device, a TFT and a method for forming the same The method includes that arranging a first insulating layer on a gate, stacking an oxide semiconductor layer and a buffer layer in order on the first insulating layer, arranging as source on the oxide semiconductor layer and a drain on the buffer layer, and plasma processing or heating in oxygen atmosphere the buffer layer which does not directly contact the source and the drain. Therefore, the present invention is capable of preventing the oxide semiconductor layer from damage in follow-up processes to assure stability of the TFT and display quality of the active-matrix panel display device.

Abstract: A fabricating method of an active device array substrate is provided. The active device array substrate has at least one patterned conductive layer. The patterned conductive layer includes a copper layer. A cross-section of the copper layer which is parallel to a normal line direction of the copper layer includes a first trapezoid and a second trapezoid stacked on the first trapezoid. A base angle of the first trapezoid and a base angle of the second trapezoid are acute angles, and a difference between the base angle of the first trapezoid and the base angle of the second trapezoid is from about 5° to about 30°.

Abstract: A pixel structure disposed on a substrate including a thin film transistor (TFT), a passivation layer, and a pixel electrode is provided. The TFT includes a gate, a dielectric layer, a channel layer, and a source/drain sequentially disposed on the substrate. The source/drain is disposed on a portion of the channel layer and has a semiconductor layer, a barrier layer and a metal layer. The barrier layer is disposed on a portion of the semiconductor layer. The metal layer is disposed on the barrier layer. The barrier layer is in contact with the semiconductor layer and the metal layer. Both of the metal layer and the barrier layer are positioned within a projection area of the semiconductor layer. The passivation layer covers the TFT and the dielectric layer and has a first opening exposing the source/drain. The pixel electrode is electrically connected to the TFT through the first opening.

Abstract: An active device array substrate has at least one patterned conductive layer. The patterned conductive layer includes a copper layer. A cross-section of the copper layer which is parallel to a normal line direction of the copper layer includes a first trapezoid and a second trapezoid stacked on the first trapezoid. A base angle of the first trapezoid and a base angle of the second trapezoid are acute angles, and a difference between the base angle of the first trapezoid and the base angle of the second trapezoid is from about 5° to about 30°.

Abstract: A pixel structure disposed on a substrate including a thin film transistor (TFT), a bottom capacitor electrode, a dielectric layer, an upper capacitor electrode, a passivation layer, and a pixel electrode is provided. The TFT having a source/drain and the bottom capacitor electrode are disposed on the substrate. The dielectric layer is disposed on the bottom capacitor electrode. The upper capacitor electrode has a semiconductor layer, a barrier layer, and a metal layer. The semiconductor layer is disposed on the dielectric layer above the bottom capacitor electrode. The barrier layer is disposed on the semiconductor layer. The metal layer whose material includes copper, a copper alloy, or a combination thereof is disposed on the barrier layer. The passivation layer covers the TFT and the upper capacitor electrode and has a first opening exposing the source/drain. The pixel electrode is electrically connected to the TFT through the first opening.

Abstract: An active device array substrate has at least one patterned conductive layer. The patterned conductive layer includes a copper layer. A cross-section of the copper layer which is parallel to a normal line direction of the copper layer includes a first trapezoid and a second trapezoid stacked on the first trapezoid. A base angle of the first trapezoid and a base angle of the second trapezoid are acute angles, and a difference between the base angle of the first trapezoid and the base angle of the second trapezoid is from about 5° to about 30°.

Abstract: A display element and a method of manufacturing the same are provided. The method comprises the following steps: forming a first patterned conducting layer with a gate on a substrate and a dielectric layer thereon; forming a patterned semiconductor layer on the dielectric layer, wherein the patterned semiconductor layer has a channel region, a source and a drain, and wherein the source and the drain lie on the opposite sides of the channel region; selectively depositing a barrier layer, which only wraps the patterned semiconductor layer; forming a second patterned conducting layer on the barrier layer and above the source and the drain. In the display element manufactured by the method, the barrier layer only wraps the patterned semiconductor layer.

Abstract: A display element and a method of manufacturing the same are provided. The method comprises the following steps: forming a first patterned conducting layer with a gate on a substrate and a dielectric layer thereon; forming a patterned semiconductor layer on the dielectric layer, wherein the patterned semiconductor layer has a channel region, a source and a drain, and wherein the source and the drain lie on the opposite sides of the channel region; selectively depositing a barrier layer, which only wraps the patterned semiconductor layer; forming a second patterned conducting layer on the barrier layer and above the source and the drain. In the display element manufactured by the method, the barrier layer only wraps the patterned semiconductor layer.

Abstract: A display element and a method of manufacturing the same are provided. The method comprises the following steps: forming a first patterned conducting layer with a gate on a substrate and a dielectric layer thereon; forming a patterned semiconductor layer on the dielectric layer, wherein the patterned semiconductor layer has a channel region, a source and a drain, and wherein the source and the drain lie on the opposite sides of the channel region; selectively depositing a barrier layer, which only wraps the patterned semiconductor layer; forming a second patterned conducting layer on the barrier layer and above the source and the drain. In the display element manufactured by the method, the barrier layer only wraps the patterned semiconductor layer.