Patents by Inventor Po-Lun Cheng

Po-Lun Cheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11982944
    Abstract: A method of lithography process is provided. The method includes forming a conductive layer over a reticle. The method includes applying ionized particles to the reticle by a discharging device. The method includes forming a photoresist layer over a semiconductor substrate. The method includes securing the semiconductor substrate by a wafer electrostatic-clamp. The method also includes patterning the photoresist layer by emitting radiation from a radiation source via the reticle.
    Type: Grant
    Filed: May 31, 2023
    Date of Patent: May 14, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hsiao-Lun Chang, Chueh-Chi Kuo, Tsung-Yen Lee, Tzung-Chi Fu, Li-Jui Chen, Po-Chung Cheng, Che-Chang Hsu
  • Patent number: 9761687
    Abstract: A method of forming a gate dielectric layer for a MOS transistor includes the following steps. A gate dielectric layer is formed on a substrate. A nitridation process is performed on the gate dielectric layer. A multi-step post nitridation annealing process including two oxygen-containing annealing steps with different respective annealing temperatures is performed on the gate dielectric layer.
    Type: Grant
    Filed: January 4, 2015
    Date of Patent: September 12, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Han-Lin Hsu, Po-Lun Cheng, Chun-Liang Chen, Meng-Che Yeh, Shih-Jung Tu
  • Patent number: 9761693
    Abstract: A method for fabricating semiconductor device is disclosed. First, a substrate is provided, a gate structure is formed on the substrate, a spacer is formed around the gate structure, and an epitaxial layer is formed in the substrate adjacent to the spacer. Preferably, the step of forming the epitaxial layer further includes: forming a buffer layer in the substrate; forming a bulk layer on the buffer layer; forming a linear gradient cap on the bulk layer, and forming a silicon cap on the linear gradient cap. Preferably, the etching to deposition ratio of the linear gradient cap is greater than 50% and less than 100%.
    Type: Grant
    Filed: November 1, 2016
    Date of Patent: September 12, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yin-Cheng Cheng, Po-Lun Cheng, Ming-Chih Hsu, Ya-Chen Chang, Hsien-Yao Chu
  • Publication number: 20170207079
    Abstract: A substrate cleaning method is provided. A substrate is provided, followed by performing a first pre-cleaning process with a first rotation speed and a first duration time. After the first pre-cleaning process, a second pre-cleaning process is performed with a second rotation speed and a second duration time, wherein the second rotation speed is greater than the first rotation speed. After the second pre-cleaning process, a cleaning process is performed by using a chemical agent with a cleaning rotation speed.
    Type: Application
    Filed: January 15, 2016
    Publication date: July 20, 2017
    Inventors: Chia-Ming Lee, Kuo-Wei Chih, Chen-Hsu Hung, Chun-Li Lin, Chia-Yen Hsu, Tsung-Hsun Tsai, Po-Lun Cheng
  • Publication number: 20170186607
    Abstract: The method of forming a semiconductor device is provided. A substrate having an exposed oxide layer is provided. A nitridation process is performed for the oxide layer. After the nitridation process, a plasma treatment containing an inert gas is performed for the oxide layer. A conductive layer is formed on the oxide layer.
    Type: Application
    Filed: December 28, 2015
    Publication date: June 29, 2017
    Inventors: Yi-Ting Kuo, Shih-Jung Tu, Chun-Liang Chen, Po-Lun Cheng
  • Publication number: 20170098558
    Abstract: An acid replenishing system includes an acid tank, a draining apparatus, an acid replenishing apparatus, and a control unit. The acid tank contains a used acid solution. The draining apparatus drains an amount of the used acid solution from the acid tank. The acid replenishing apparatus replenishes an amount of a replenishing acid into the acid tank. The control unit controls the draining apparatus and the acid replenishing apparatus to perform a plurality of acid replenishing stages, so a total set amount of the replenishing acid to be added into the acid tank has been replenished.
    Type: Application
    Filed: November 6, 2015
    Publication date: April 6, 2017
    Inventors: Tzung-Wu Hou, Po-Lun Cheng, Meng-Che Yeh, Feng-Nan Chu
  • Publication number: 20170047427
    Abstract: A method for fabricating semiconductor device is disclosed. First, a substrate is provided, a gate structure is formed on the substrate, a spacer is formed around the gate structure, and an epitaxial layer is formed in the substrate adjacent to the spacer. Preferably, the step of forming the epitaxial layer further includes: forming a buffer layer in the substrate; forming a bulk layer on the buffer layer; forming a linear gradient cap on the bulk layer, and forming a silicon cap on the linear gradient cap. Preferably, the etching to deposition ratio of the linear gradient cap is greater than 50% and less than 100%.
    Type: Application
    Filed: November 1, 2016
    Publication date: February 16, 2017
    Inventors: Yin-Cheng Cheng, Po-Lun Cheng, Ming-Chih Hsu, Ya-Chen Chang, Hsien-Yao Chu
  • Publication number: 20160196971
    Abstract: A method of forming a gate dielectric layer for a MOS transistor includes the following steps. A gate dielectric layer is formed on a substrate. A nitrdation process is performed on the gate dielectric layer. A multi-step post nitridation annealing process including two oxygen-containing annealing steps with different respective annealing temperatures is performed on the gate dielectric layer.
    Type: Application
    Filed: January 4, 2015
    Publication date: July 7, 2016
    Inventors: Han-Lin Hsu, Po-Lun Cheng, Chun-Liang Chen, Meng-Che Yeh, Shih-Jung Tu
  • Publication number: 20160155818
    Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; and forming an epitaxial layer on the substrate, in which an etching to deposition ratio of the epitaxial layer is greater than 50%.
    Type: Application
    Filed: November 27, 2014
    Publication date: June 2, 2016
    Inventors: Yin-Cheng Cheng, Po-Lun Cheng, Ming-Chih Hsu, Ya-Chen Chang, Hsien-Yao Chu
  • Patent number: 9148039
    Abstract: A motor assembly includes a working part, a synchronous motor having a shaft, and a mechanical coupling joining the working part to the motor. The coupling has two driving teeth fixed relative to the shaft, two driven teeth fixed relative to the working part, and two middle members. The coupling provides a predetermined range of angular movement between the motor and the working part. The middle members are circumferentially distributed between the two driving teeth and between the two driven teeth, thereby each of the middle members is movable by the driving teeth to contact the driven teeth and provides an interference between a driving tooth and a driven tooth to drive the working part.
    Type: Grant
    Filed: November 9, 2011
    Date of Patent: September 29, 2015
    Assignee: JOHNSON ELECTRIC S.A
    Inventors: Zhi Ping Fu, Po Lun Cheng, Min Li
  • Patent number: 8716092
    Abstract: A method for fabricating a MOS transistor is disclosed. First, a semiconductor substrate having a gate thereon is provided. A spacer is then formed on the sidewall of the gate, and two recesses are formed adjacent to the spacer and within the semiconductor substrate. Next, the spacer is thinned, and epitaxial layer is grown in each of the two recesses. By thinning the spacer before the epitaxial layer is formed, the present invention could stop the epitaxial layer to grow against the sidewall of the spacer, thereby preventing problem such as Ion degradation.
    Type: Grant
    Filed: December 21, 2011
    Date of Patent: May 6, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Po-Lun Cheng, Pin-Chien Chu
  • Patent number: 8613605
    Abstract: A centrifugal pump includes a pump unit and a drive unit. The pump unit includes a volute and an impeller disposed in the volute. The drive unit includes a stator and a rotor having a shaft. The volute includes an inlet, an outlet and a chamber in communication with the inlet and outlet. The shaft of the rotor extends into the chamber of the volute and the impeller is attached to and driven by the shaft. The volute further includes a transition part connected between the outlet and the chamber and communicating the outlet with the chamber. The axis of the transition part is angled to the axis of the outlet. The transition part is configured to improve the effect of fluid turbulence to thereby reduce noise, especially in the air-water stage.
    Type: Grant
    Filed: April 22, 2010
    Date of Patent: December 24, 2013
    Assignee: Johnson Electric S.A.
    Inventors: John Hammar, Po Lun Cheng, Min Li
  • Patent number: 8415723
    Abstract: A spacer structure contains a carbon-containing oxide film positioned on a gate sidewall and a nitride film covering the carbon-containing oxide film. The carbon-containing oxide film has low etch rate so that the spacer structure can have a good profile during etching the carbon-containing oxide film.
    Type: Grant
    Filed: June 7, 2012
    Date of Patent: April 9, 2013
    Assignee: United Microelectronics Corp.
    Inventors: Po-Lun Cheng, Che-Hung Liu
  • Patent number: 8288802
    Abstract: A spacer structure contains a carbon-containing oxynitride film positioned on a gate sidewall and a nitride film covering the carbon-containing oxide film. The carbon-containing oxynitride film has low etch rate so that the spacer structure can have a good profile during etching the carbon-containing oxynitride film.
    Type: Grant
    Filed: April 19, 2006
    Date of Patent: October 16, 2012
    Assignee: United Microelectronics Corp.
    Inventors: Po-Lun Cheng, Che-Hung Liu
  • Publication number: 20120241824
    Abstract: A spacer structure contains a carbon-containing oxide film positioned on a gate sidewall and a nitride film covering the carbon-containing oxide film. The carbon-containing oxide film has low etch rate so that the spacer structure can have a good profile during etching the carbon-containing oxide film.
    Type: Application
    Filed: June 7, 2012
    Publication date: September 27, 2012
    Inventors: Po-Lun Cheng, Che-Hung Liu
  • Publication number: 20120112567
    Abstract: A motor assembly includes a working part, a synchronous motor having a shaft, and a mechanical coupling joining the working part to the motor. The coupling has two driving teeth fixed relative to the shaft, two driven teeth fixed relative to the working part, and two middle members. The coupling provides a predetermined range of angular movement between the motor and the working part. The middle members are circumferentially distributed between the two driving teeth and between the two driven teeth, thereby each of the middle members is movable by the driving teeth to contact the driven teeth and provides an interference between a driving tooth and a driven tooth to drive the working part.
    Type: Application
    Filed: November 9, 2011
    Publication date: May 10, 2012
    Inventors: Zhi Ping FU, Po Lun CHENG, Min LI
  • Publication number: 20120094460
    Abstract: A method for fabricating a MOS transistor is disclosed. First, a semiconductor substrate having a gate thereon is provided. A spacer is then formed on the sidewall of the gate, and two recesses are formed adjacent to the spacer and within the semiconductor substrate. Next, the spacer is thinned, and epitaxial layer is grown in each of the two recesses. By thinning the spacer before the epitaxial layer is formed, the present invention could stop the epitaxial layer to grow against the sidewall of the spacer, thereby preventing problem such as Ion degradation.
    Type: Application
    Filed: December 21, 2011
    Publication date: April 19, 2012
    Inventors: Po-Lun Cheng, Pin-Chien Chu
  • Patent number: 8106466
    Abstract: A method for fabricating a MOS transistor is disclosed. First, a semiconductor substrate having a gate thereon is provided. A spacer is then formed on the sidewall of the gate, and two recesses are formed adjacent to the spacer and within the semiconductor substrate. Next, the spacer is thinned, and epitaxial layer is grown in each of the two recesses. By thinning the spacer before the epitaxial layer is formed, the present invention could stop the epitaxial layer to grow against the sidewall of the spacer, thereby preventing problem such as Ion degradation.
    Type: Grant
    Filed: August 10, 2008
    Date of Patent: January 31, 2012
    Assignee: United Microelectronics Corp.
    Inventors: Po-Lun Cheng, Pin-Chien Chu
  • Patent number: 8076194
    Abstract: A method of fabricating a MOS transistor is disclosed. The method includes the steps of: providing a semiconductor substrate; forming at least a gate on the semiconductor substrate; forming a protective layer on the semiconductor substrate, and the protective layer covering the surface of the gate; forming at least a recess within the semiconductor substrate adjacent to the gate; forming an epitaxial layer in the recess, wherein the top surface of the epitaxial layer is above the surface of the semiconductor substrate; and forming a spacer on the sidewall of the gate and on a portion of the epitaxial layer, wherein a contact surface of the epitaxial layer and the spacer is above the surface of the semiconductor substrate.
    Type: Grant
    Filed: May 18, 2010
    Date of Patent: December 13, 2011
    Assignee: United Microelectronics Corp.
    Inventors: Chu-Yin Tseng, Shih-Chieh Hsu, Chih-Chiang Wu, Shyh-Fann Ting, Po-Lun Cheng, Hsuan-Hsu Chen
  • Patent number: D1027182
    Type: Grant
    Filed: August 15, 2022
    Date of Patent: May 14, 2024
    Assignees: Interface Technology (ChengDu) Co., Ltd., INTERFACE OPTOELECTRONICS (SHENZHEN) CO., LTD., GENERAL INTERFACE SOLUTION LIMITED
    Inventors: Chun-Ming Cheng, Chih-Lin Liao, Yi-Chia Chiu, Chun-Ta Chen, Po-Lun Chen