Patents by Inventor Po-Lun Cheng
Po-Lun Cheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8076194Abstract: A method of fabricating a MOS transistor is disclosed. The method includes the steps of: providing a semiconductor substrate; forming at least a gate on the semiconductor substrate; forming a protective layer on the semiconductor substrate, and the protective layer covering the surface of the gate; forming at least a recess within the semiconductor substrate adjacent to the gate; forming an epitaxial layer in the recess, wherein the top surface of the epitaxial layer is above the surface of the semiconductor substrate; and forming a spacer on the sidewall of the gate and on a portion of the epitaxial layer, wherein a contact surface of the epitaxial layer and the spacer is above the surface of the semiconductor substrate.Type: GrantFiled: May 18, 2010Date of Patent: December 13, 2011Assignee: United Microelectronics Corp.Inventors: Chu-Yin Tseng, Shih-Chieh Hsu, Chih-Chiang Wu, Shyh-Fann Ting, Po-Lun Cheng, Hsuan-Hsu Chen
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Patent number: 8067282Abstract: A method for selective formation of trenches is disclosed. First, a substrate is provided. The substrate includes a first semiconductor element and a second semiconductor element. The first semiconductor element has a dopant. Second, a wet etching procedure is carried out to selectively form a pair of trenches in the substrate around the second semiconductor element, a first source/drain ion implantation is selectively carried out on the first semiconductor element, or a second source/drain ion implantation is selectively carried out on the second semiconductor element.Type: GrantFiled: October 8, 2009Date of Patent: November 29, 2011Assignee: United Microelectronics Corp.Inventors: Pin-Chien Chu, Shin-Chi Chen, Po-Lun Cheng
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Publication number: 20110086479Abstract: A method for selective formation of trenches is disclosed. First, a substrate is provided. The substrate includes a first semiconductor element and a second semiconductor element. The first semiconductor element has a dopant. Second, a wet etching procedure is carried out to selectively form a pair of trenches in the substrate around the second semiconductor element, a first source/drain ion implantation is selectively carried out on the first semiconductor element, or a second source/drain ion implantation is selectively carried out on the second semiconductor element.Type: ApplicationFiled: October 8, 2009Publication date: April 14, 2011Inventors: Pin-Chien Chu, Shin-Chi Chen, Po-Lun Cheng
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Publication number: 20100272562Abstract: A centrifugal pump includes a pump unit and a drive unit. The pump unit includes a volute and an impeller disposed in the volute. The drive unit includes a stator and a rotor having a shaft. The volute includes an inlet, an outlet and a chamber in communication with the inlet and outlet. The shaft of the rotor extends into the chamber of the volute and the impeller is attached to and driven by the shaft. The volute further includes a transition part connected between the outlet and the chamber and communicating the outlet with the chamber. The axis of the transition part is angled to the axis of the outlet. The transition part is configured to improve the effect of fluid turbulence to thereby reduce noise, especially in the air-water stage.Type: ApplicationFiled: April 22, 2010Publication date: October 28, 2010Inventors: John HAMMAR, Po Lun Cheng, Min Li
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Publication number: 20100227445Abstract: A method of fabricating a MOS transistor is disclosed. The method includes the steps of: providing a semiconductor substrate; forming at least a gate on the semiconductor substrate; forming a protective layer on the semiconductor substrate, and the protective layer covering the surface of the gate; forming at least a recess within the semiconductor substrate adjacent to the gate; forming an epitaxial layer in the recess, wherein the top surface of the epitaxial layer is above the surface of the semiconductor substrate; and forming a spacer on the sidewall of the gate and on a portion of the epitaxial layer, wherein a contact surface of the epitaxial layer and the spacer is above the surface of the semiconductor substrate.Type: ApplicationFiled: May 18, 2010Publication date: September 9, 2010Inventors: Chu-Yin Tseng, Shih-Chieh Hsu, Chih-Chiang Wu, Shyh-Fann Ting, Po-Lun Cheng, Hsuan-Hsu Chen
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Patent number: 7745847Abstract: The present invention provides a method for fabricating a metal oxide semiconductor transistor. First, a semiconductor substrate is provided and at least a gate is formed on the semiconductor substrate. A protective layer is then formed on the semiconductor substrate and the gate. Subsequently, at least a recess is formed in the semiconductor substrate adjacent to the gate, and then an epitaxial layer is formed in the recess. A lightly doped region is formed in the semiconductor substrate adjacent to the gate. Finally, a spacer is formed on the sidewall of the gate.Type: GrantFiled: August 9, 2007Date of Patent: June 29, 2010Assignee: United Microelectronics Corp.Inventors: Chu-Yin Tseng, Shih-Chieh Hsu, Chih-Chiang Wu, Shyh-Fann Ting, Po-Lun Cheng, Hsuan-Hsu Chen
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Publication number: 20100032715Abstract: A method for fabricating a MOS transistor is disclosed. First, a semiconductor substrate having a gate thereon is provided. A spacer is then formed on the sidewall of the gate, and two recesses are formed adjacent to the spacer and within the semiconductor substrate. Next, the spacer is thinned, and epitaxial layer is grown in each of the two recesses. By thinning the spacer before the epitaxial layer is formed, the present invention could stop the epitaxial layer to grow against the sidewall of the spacer, thereby preventing problem such as Ion degradation.Type: ApplicationFiled: August 10, 2008Publication date: February 11, 2010Inventors: Po-Lun Cheng, Pin-Chien Chu
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Patent number: 7592231Abstract: A method of fabricating a MOS transistor is described. A substrate is provided, and then a composite layer for forming a gate structure and a carbon-containing mask material layer are formed thereon in turn, wherein the carbon-containing mask material layer is formed with a carbon-containing precursor gas and a reaction gas. The carbon-containing mask material layer and the composite layer are patterned into a carbon-containing hard mask layer and a gate structure, respectively. A spacer is formed on the sidewalls of the gate structure and the carbon-containing hard mask layer. A passivation layer is formed over the substrate, and then a portion of the passivation layer is removed to expose a portion of the substrate. A doped epitaxial layer is formed on the exposed portion of the substrate.Type: GrantFiled: August 1, 2006Date of Patent: September 22, 2009Assignee: United Microelectronics Corp.Inventors: Po-Lun Cheng, Che-Hung Liu
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Publication number: 20090108291Abstract: A semiconductor device including a gate structure, two doped regions, and two buffer layers is provided. The gate structure is disposed on a substrate. The two doped regions are made of boron doped silicon germanium (SiGeB) and are disposed in the substrate at both sides of the gate structure. The two buffer layers are made of carbon doped silicon germanium (SiGeC) and are respectively disposed between the two doped regions and the substrate.Type: ApplicationFiled: October 26, 2007Publication date: April 30, 2009Applicant: UNITED MICROELECTRONICS CORP.Inventors: Po-Lun Cheng, Pin-Chien Chu
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Publication number: 20090039389Abstract: The present invention provides a method for fabricating a metal oxide semiconductor transistor. First, a semiconductor substrate is provided and at least a gate is formed on the semiconductor substrate. A protective layer is then formed on the semiconductor substrate and the gate. Subsequently, at least a recess is formed in the semiconductor substrate adjacent to the gate, and then an epitaxial layer is formed in the recess. A lightly doped region is formed in the semiconductor substrate adjacent to the gate. Finally, a spacer is formed on the sidewall of the gate.Type: ApplicationFiled: August 9, 2007Publication date: February 12, 2009Inventors: Chu-Yin Tseng, Shih-Chieh Hsu, Chih-Chiang Wu, Shyh-Fann Ting, Po-Lun Cheng, Hsuan-Hsu Chen
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Patent number: 7456087Abstract: A semiconductor device is provided. The semiconductor device comprises a substrate, a gate structure, a spacer, a first poly-SiGe layer being boron-doped and a second poly-SiGe layer being boron-doped. The substrate has two openings and the gate structure is disposed on the substrate between the openings. The spacer is disposed on the sidewalls of the gate structure and above a portion of the openings. The first poly-SiGe layer is disposed on the surface of the openings in the substrate. The second poly-SiGe layer is disposed on the first poly-SiGe layer, and the top of the second poly-SiGe layer is higher than the surface of the substrate. Moreover, the boron concentration in the first poly-SiGe layer is lower than that in the second poly-SiGe layer.Type: GrantFiled: February 9, 2007Date of Patent: November 25, 2008Assignee: United Microelectronics Corp.Inventor: Po-Lun Cheng
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Publication number: 20080233722Abstract: A method of forming a selective area semiconductor compound epitaxy layer is provided. The method includes the step of using two silicon-containing precursors as gas source for implementing a process of manufacturing the selective area semiconductor compound epitaxy layer, so as to form a semiconductor compound epitaxy layer on an exposed monocrystalline silicon region of a substrate.Type: ApplicationFiled: March 23, 2007Publication date: September 25, 2008Applicant: UNITED MICROELECTRONICS CORP.Inventors: Chin-I Liao, Chin-Cheng Chien, Hou-Jun Wu, Po-Lun Cheng
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Publication number: 20080191206Abstract: A semiconductor device is provided. The semiconductor device comprises a substrate, a gate structure, a spacer, a first poly-SiGe layer being boron-doped and a second poly-SiGe layer being boron-doped. The substrate has two openings and the gate structure is disposed on the substrate between the openings. The spacer is disposed on the sidewalls of the gate structure and above a portion of the openings. The first poly-SiGe layer is disposed on the surface of the openings in the substrate. The second poly-SiGe layer is disposed on the first poly-SiGe layer, and the top of the second poly-SiGe layer is higher than the surface of the substrate. Moreover, the boron concentration in the first poly-SiGe layer is lower than that in the second poly-SiGe layer.Type: ApplicationFiled: February 9, 2007Publication date: August 14, 2008Applicant: UNITED MICROELECTRONICS CORP.Inventor: Po-Lun Cheng
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Publication number: 20080176390Abstract: A method for forming a carbon-containing silicon nitride layer with superior uniformity by low pressure chemical vapor deposition (LPCVD) using disilane, ammonia and at least one carbon-source precursor as reactant gases is provided.Type: ApplicationFiled: March 26, 2008Publication date: July 24, 2008Applicant: UNITED MICROELECTRONICS CORP.Inventor: Po-Lun Cheng
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Patent number: 7402496Abstract: A complementary metal-oxide-semiconductor (CMOS) device includes a substrate with a first active region and a second active region; a first gate structure and a second gate structure, respectively disposed on the first active region and the second active region; a first spacer structure and a second spacer structure respectively disposed on sidewalls of the first gate structure and the second gate structure; a first LDD and a second LDD respectively disposed in the substrate at both sides of the first gate structure and the second gate structure; an epitaxial material layer, disposed in the first active region and located on a side of the first LDD; and a passivation layer, disposed on the first gate structure, the first spacer structure, and the first LDD and covering the second active region, wherein the passivation layer comprises a carbon-containing oxynitride layer.Type: GrantFiled: September 11, 2006Date of Patent: July 22, 2008Assignee: United Microelectronics Corp.Inventors: Che-Hung Liu, Po-Lun Cheng, Chun-An Lin, Li-Yuen Tang, Hung-Lin Shih, Ming-Chi Fan, Hsien-Liang Meng, Jih-Shun Chiang
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Publication number: 20080171412Abstract: Fabrication methods for a MOS device and a CMOS device are provided. A substrate is provided with a gate structure formed on the substrate, a lightly-doped drain (LDD) region formed near sides of the gate structure in the substrate and a spacer wall formed on sidewalls of the gate structure and covering a part of the LDD region. A protection layer is formed for covering the gate structure, the LDD region and the spacer wall. A part of the protection layer is removed. Another part of the protection layer on the gate structure and the spacer wall is reserved. A part of the surface of the substrate is exposed. The exposed surface of the substrate is removed for forming a trench. A pre-clean step, including an oxygen plasma process, is performed on the bottom of the trench. An epitaxy material layer is formed in the trench.Type: ApplicationFiled: January 12, 2007Publication date: July 17, 2008Applicant: UNITED MICROELECTRONICS CORP.Inventors: Po-Lun Cheng, Che-Hung Liu
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Publication number: 20080116525Abstract: A complementary metal-oxide-semiconductor (CMOS) device includes a substrate with a first active region and a second active region; a first gate structure and a second gate structure, respectively disposed on the first active region and the second active region; a first spacer structure and a second spacer structure respectively disposed on sidewalls of the first gate structure and the second gate structure; a first LDD and a second LDD respectively disposed in the substrate at both sides of the first gate structure and the second gate structure; an epitaxial material layer, disposed in the first active region and located on a side of the first LDD; and a passivation layer, disposed on the first gate structure, the first spacer structure, and the first LDD and covering the second active region, wherein the passivation layer comprises a carbon-containing oxynitride layer.Type: ApplicationFiled: January 31, 2008Publication date: May 22, 2008Applicant: UNITED MICROELECTRONICS CORP.Inventors: Che-Hung Liu, Po-Lun Cheng, Chun-An Lin, Li-Yuen Tang, Hung-Lin Shih, Ming-Chi Fan, Hsien-Liang Meng, Jih-Shun Chiang
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Patent number: 7371649Abstract: A method for forming a carbon-containing silicon nitride layer with superior uniformity by low pressure chemical vapor deposition (LPCVD) using disilane, ammonia and at least one carbon-source precursor as reactant gases is provided.Type: GrantFiled: September 13, 2006Date of Patent: May 13, 2008Assignee: United Microelectronics Corp.Inventor: Po-Lun Cheng
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Publication number: 20080061366Abstract: A complementary metal-oxide-semiconductor (CMOS) device includes a substrate with a first active region and a second active region; a first gate structure and a second gate structure, respectively disposed on the first active region and the second active region; a first spacer structure and a second spacer structure respectively disposed on sidewalls of the first gate structure and the second gate structure; a first LDD and a second LDD respectively disposed in the substrate at both sides of the first gate structure and the second gate structure; an epitaxial material layer, disposed in the first active region and located on a side of the first LDD; and a passivation layer, disposed on the first gate structure, the first spacer structure, and the first LDD and covering the second active region, wherein the passivation layer comprises a carbon-containing oxynitride layer.Type: ApplicationFiled: September 11, 2006Publication date: March 13, 2008Applicant: UNITED MICROELECTRONICS CORP.Inventors: Che-Hung Liu, Po-Lun Cheng, Chun-An Lin, Li-Yuen Tang, Hung-Lin Shih, Ming-Chi Fan, Hsien-Liang Meng, Jih-Shun Chiang
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Patent number: 7335607Abstract: A method of forming a gate dielectric is described. A plasma treatment process is performed to form a dielectric structure on a substrate, wherein the dielectric structure having a graded dielectric constant value that decreases gradually in a direction toward the substrate.Type: GrantFiled: January 20, 2006Date of Patent: February 26, 2008Assignee: United Microelectronics Corp.Inventors: Po-Lun Cheng, Li-Wei Cheng