Patents by Inventor Po-Lun Cheng

Po-Lun Cheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7329591
    Abstract: A method for forming a silicon-containing film is described. A substrate is placed in a reaction chamber, and then a silicon-containing gas is introduced into the reaction chamber to conduct a CVD process and deposit a silicon-containing film on the substrate. During the CVD process, the temperature of at least the top inner surface of the reaction chamber is controlled below 50° C.
    Type: Grant
    Filed: February 21, 2006
    Date of Patent: February 12, 2008
    Assignee: United Microelectronics Corp.
    Inventors: Che-Hung Liu, Po-Lun Cheng, Hwei-Lin Chuang, Chun-An Lin
  • Publication number: 20080032468
    Abstract: A method of fabricating a MOS transistor is described. A substrate is provided, and then a composite layer for forming a gate structure and a carbon-containing mask material layer are formed thereon in turn, wherein the carbon-containing mask material layer is formed with a carbon-containing precursor gas and a reaction gas. The carbon-containing mask material layer and the composite layer are patterned into a carbon-containing hard mask layer and a gate structure, respectively. A spacer is formed on the sidewalls of the gate structure and the carbon-containing hard mask layer. A passivation layer is formed over the substrate, and then a portion of the passivation layer is removed to expose a portion of the substrate. A doped epitaxial layer is formed on the exposed portion of the substrate.
    Type: Application
    Filed: August 1, 2006
    Publication date: February 7, 2008
    Applicant: United Microelectronics Corp.
    Inventors: Po-Lun Cheng, Che-Hung Liu
  • Publication number: 20070246751
    Abstract: A spacer structure contains a carbon-containing oxynitride film positioned on a gate sidewall and a nitride film covering the carbon-containing oxide film. The carbon-containing oxynitride film has low etch rate so that the spacer structure can have a good profile during etching the carbon-containing oxynitride film.
    Type: Application
    Filed: April 19, 2006
    Publication date: October 25, 2007
    Inventors: Po-Lun Cheng, Che-Hung Liu
  • Publication number: 20070197007
    Abstract: A method for forming a silicon-containing film is described. A substrate is placed in a reaction chamber, and then a silicon-containing gas is introduced into the reaction chamber to conduct a CVD process and deposit a silicon-containing film on the substrate. During the CVD process, the temperature of at least the top inner surface of the reaction chamber is controlled below 50° C.
    Type: Application
    Filed: February 21, 2006
    Publication date: August 23, 2007
    Inventors: Che-Hung Liu, Po-Lun Cheng, Hwei-Lin Chuang, Chun-An Lin
  • Publication number: 20070059870
    Abstract: A method for forming a carbon-containing silicon nitride layer with superior uniformity by low pressure chemical vapor deposition (LPCVD) using disilane, ammonia and at least one carbon-source precursor as reactant gases is provided.
    Type: Application
    Filed: September 13, 2006
    Publication date: March 15, 2007
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventor: Po-Lun Cheng
  • Patent number: 7186605
    Abstract: A method of fabricating gates is provided. A first sacrificial layer having a first and a second gate openings therein is formed on a substrate. Next, a gate dielectric layer is formed on the substrate exposed by the first sacrificial layer. Thereafter, a second sacrificial layer is filled in the first and second gate openings. The second sacrificial layer in the first gate opening is removed, and then a first conductive layer is filled in the first gate opening as a gate of a MOS transistor of a first conductivity type. Then, the second sacrificial layer in the second gate opening is removed. A second conductive layer is filled in the second gate opening as a gate of a MOS transistor of a second conductivity type, and the first sacrificial layer is removed.
    Type: Grant
    Filed: December 17, 2004
    Date of Patent: March 6, 2007
    Assignee: United Microelectronics Corp.
    Inventors: Po-Lun Cheng, Li-Wei Cheng
  • Publication number: 20060228907
    Abstract: A method of forming a gate dielectric is described. A plasma treatment process is performed to form a dielectric structure on a substrate, wherein the dielectric structure having a graded dielectric constant value that decreases gradually in a direction toward the substrate.
    Type: Application
    Filed: January 20, 2006
    Publication date: October 12, 2006
    Inventors: Po-Lun Cheng, Li-Wei Cheng
  • Publication number: 20060226500
    Abstract: A method of forming a gate dielectric is described. A plasma treatment process is performed to form a dielectric structure on a substrate, wherein the dielectric structure having a graded dielectric constant value that decreases gradually in a direction toward the substrate.
    Type: Application
    Filed: April 6, 2005
    Publication date: October 12, 2006
    Inventors: Po-Lun Cheng, Li-Wei Cheng
  • Publication number: 20060172473
    Abstract: A substrate is provided, and a silicon dioxide thin film is formed thereon. Subsequently, an amorphous silicon thin film is formed over the silicon dioxide thin film, and a low temperature plasma nitridation process is preformed to form a nitrogen-containing amorphous silicon thin film. Following that, an oxygen annealing process is carried out to form a nitrogen-rich silicon oxynitride layer.
    Type: Application
    Filed: February 3, 2005
    Publication date: August 3, 2006
    Inventors: Po-Lun Cheng, Li-Wei Cheng
  • Publication number: 20060134842
    Abstract: A method of fabricating gates is provided. A first sacrificial layer having a first and a second gate openings therein is formed on a substrate. Next, a gate dielectric layer is formed on the substrate exposed by the first sacrificial layer. Thereafter, a second sacrificial layer is filled in the first and second gate openings. The second sacrificial layer in the first gate opening is removed, and then a first conductive layer is filled in the first gate opening as a gate of a MOS transistor of a first conductivity type. Then, the second sacrificial layer in the second gate opening is removed. A second conductive layer is filled in the second gate opening as a gate of a MOS transistor of a second conductivity type, and the first sacrificial layer is removed.
    Type: Application
    Filed: December 17, 2004
    Publication date: June 22, 2006
    Inventors: Po-Lun Cheng, Li-Wei Cheng
  • Publication number: 20030181027
    Abstract: A surface of a semiconductor wafer has a first gate oxide area and a second gate oxide area. A first gate oxide layer and a photoresist layer are formed on the surface of the semiconductor wafer. A wet etching process is performed to remove the first gate oxide layer not in the first gate oxide area on the surface of the semiconductor wafer. The photoresist layer is then removed. After performing a wet cleaning process, a second gate oxide layer is formed on the surface of the semiconductor wafer. Finally, a two-step polysilicon deposition process is performed, the resultant polysilicon layer covering the first gate oxide area and the second gate oxide layer. The two-step polysilicon deposition process involves a first-step low temperature amorphous silicon (&agr;-Si) deposition process, and a second-step high temperature polysilicon deposition process so as to avoid the formation of particles and defects when forming the polysilicon layer.
    Type: Application
    Filed: March 25, 2002
    Publication date: September 25, 2003
    Inventors: Chao-Hu Liang, Chih-Hung Chen, Yu-Shan Tai, Po-Lun Cheng