Patents by Inventor Prashant R. Chandra
Prashant R. Chandra has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20210117130Abstract: A method is performed by a first server on a chip (SoC) node that is one instance of a plurality of nodes within a cluster of nodes. An operation is performed for determine if a second one of the SoC nodes in the cluster has data stored thereon corresponding to a data identifier in response to receiving a data retrieval request including the data identifier. An operation is performed for determining if a remote memory access channel exists between the SoC node and the second one of the SoC nodes. An operation is performed for access the data from the second one of the SoC nodes using the remote memory access channel after determine that the second one of the SoC nodes has the data stored thereon and that the remote memory access channel exists between the SoC node and the second one of the SoC nodes.Type: ApplicationFiled: November 4, 2020Publication date: April 22, 2021Inventors: Mark Bradley Davis, Prashant R. Chandra
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Patent number: 10877695Abstract: A method is performed by a first server on a chip (SoC) node that is one instance of a plurality of nodes within a cluster of nodes. An operation is performed for determine if a second one of the SoC nodes in the cluster has data stored thereon corresponding to a data identifier in response to receiving a data retrieval request including the data identifier. An operation is performed for determining if a remote memory access channel exists between the SoC node and the second one of the SoC nodes. An operation is performed for access the data from the second one of the SoC nodes using the remote memory access channel after determine that the second one of the SoC nodes has the data stored thereon and that the remote memory access channel exists between the SoC node and the second one of the SoC nodes.Type: GrantFiled: November 21, 2018Date of Patent: December 29, 2020Assignee: III Holdings 2, LLCInventors: Mark Bradley Davis, Prashant R. Chandra
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Publication number: 20200159449Abstract: A method is performed by a first server on a chip (SoC) node that is one instance of a plurality of nodes within a cluster of nodes. An operation is performed for determine if a second one of the SoC nodes in the cluster has data stored thereon corresponding to a data identifier in response to receiving a data retrieval request including the data identifier. An operation is performed for determining if a remote memory access channel exists between the SoC node and the second one of the SoC nodes. An operation is performed for access the data from the second one of the SoC nodes using the remote memory access channel after determine that the second one of the SoC nodes has the data stored thereon and that the remote memory access channel exists between the SoC node and the second one of the SoC nodes.Type: ApplicationFiled: November 21, 2018Publication date: May 21, 2020Inventors: Mark Bradley Davis, Prashant R. Chandra
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Publication number: 20190166046Abstract: Described are embodiments of methods, apparatuses, and systems for multi-protocol tunneling across a multi-protocol I/O interconnect of computer apparatus. A multi-protocol I/O interconnect may include a switching fabric operatively coupled to a first protocol-specific controller and a second protocol-specific controller, and may be configured to simultaneously route packets of the first protocol to the first protocol-specific controller and packets of the second protocol to the second protocol-specific controller. Other embodiments may be described and claimed.Type: ApplicationFiled: September 21, 2018Publication date: May 30, 2019Inventors: Prashant R. CHANDRA, Kevin C. KAHN
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Patent number: 10140245Abstract: A method is performed by a first server on a chip (SoC) node that is one instance of a plurality of nodes within a cluster of nodes. An operation is performed for determine if a second one of the SoC nodes in the cluster has data stored thereon corresponding to a data identifier in response to receiving a data retrieval request including the data identifier. An operation is performed for determining if a remote memory access channel exists between the SoC node and the second one of the SoC nodes. An operation is performed for access the data from the second one of the SoC nodes using the remote memory access channel after determine that the second one of the SoC nodes has the data stored thereon and that the remote memory access channel exists between the SoC node and the second one of the SoC nodes.Type: GrantFiled: November 21, 2016Date of Patent: November 27, 2018Assignee: III HOLDINGS 2, LLCInventors: Mark Bradley Davis, Prashant R. Chandra
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Patent number: 10110480Abstract: Described are embodiments of methods, apparatuses, and systems for multi-protocol tunneling across a multi-protocol I/O interconnect of computer apparatus. A multi-protocol I/O interconnect may include a switching fabric operatively coupled to a first protocol-specific controller and a second protocol-specific controller, and may be configured to simultaneously route packets of the first protocol to the first protocol-specific controller and packets of the second protocol to the second protocol-specific controller. Other embodiments may be described and claimed.Type: GrantFiled: January 17, 2017Date of Patent: October 23, 2018Assignee: Intel CorporationInventors: Prashant R. Chandra, Kevin C. Kahn
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Patent number: 9697159Abstract: Described are embodiments of methods, apparatuses, and systems for time synchronization of a multi-protocol I/O interconnect of computer apparatus. A method for synchronizing time across the multi-protocol I/O interconnect may include determining a first local time at a first port of a first switch of a switching fabric of a multi-protocol interconnect and a second local time at a second port of a second switch of the switching fabric, calculating an offset value based at least in part on a difference between the first local time and the second local time, and adjusting the second local time by the offset value. Other embodiments may be described and claimed.Type: GrantFiled: December 27, 2011Date of Patent: July 4, 2017Assignee: Intel CorporationInventors: Prashant R. Chandra, Vladimir Yudovich, Eran Galil, Efraim Kugman
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Patent number: 9672143Abstract: A data processing node has an inter-node messaging module including a plurality of sets of registers each defining an instance of a GET/PUT context and a plurality of data processing cores each coupled to the inter-node messaging module. Each one of the data processing cores includes a mapping function for mapping each one of a plurality of user level processes to a different one of the sets of registers and thereby to a respective GET/PUT context instance. Mapping each one of the user level processes to the different one of the sets of registers enables a particular one of the user level processes to utilize the respective GET/PUT context instance thereof for performing a GET/PUT action to a ring buffer of a different data processing node coupled to the data processing node through a fabric without involvement of an operating system of any one of the data processing cores.Type: GrantFiled: November 24, 2015Date of Patent: June 6, 2017Assignee: III HOLDINGS 2, LLCInventors: Prashant R. Chandra, Thomas A. Volpe, Mark Bradley Davis, Niall Joseph Dalton
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Patent number: 9648102Abstract: A method is performed by a first server on a chip (SoC) node that is one instance of a plurality of nodes within a cluster of nodes. An operation is performed for determine if a second one of the SoC nodes in the cluster has data stored thereon corresponding to a data identifier in response to receiving a data retrieval request including the data identifier. An operation is performed for determining if a remote memory access channel exists between the SoC node and the second one of the SoC nodes. An operation is performed for access the data from the second one of the SoC nodes using the remote memory access channel after determine that the second one of the SoC nodes has the data stored thereon and that the remote memory access channel exists between the SoC node and the second one of the SoC nodes.Type: GrantFiled: December 27, 2012Date of Patent: May 9, 2017Assignee: III Holdings 2, LLCInventors: Mark Bradley Davis, Prashant R. Chandra
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Publication number: 20170126553Abstract: Described are embodiments of methods, apparatuses, and systems for multi-protocol tunneling across a multi-protocol I/O interconnect of computer apparatus. A multi-protocol I/O interconnect may include a switching fabric operatively coupled to a first protocol-specific controller and a second protocol-specific controller, and may be configured to simultaneously route packets of the first protocol to the first protocol-specific controller and packets of the second protocol to the second protocol-specific controller. Other embodiments may be described and claimed.Type: ApplicationFiled: January 17, 2017Publication date: May 4, 2017Inventors: Prashant R. CHANDRA, Kevin C. KAHN
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Publication number: 20170068639Abstract: A method is performed by a first server on a chip (SoC) node that is one instance of a plurality of nodes within a cluster of nodes. An operation is performed for determine if a second one of the SoC nodes in the cluster has data stored thereon corresponding to a data identifier in response to receiving a data retrieval request including the data identifier. An operation is performed for determining if a remote memory access channel exists between the SoC node and the second one of the SoC nodes. An operation is performed for access the data from the second one of the SoC nodes using the remote memory access channel after determine that the second one of the SoC nodes has the data stored thereon and that the remote memory access channel exists between the SoC node and the second one of the SoC nodes.Type: ApplicationFiled: November 21, 2016Publication date: March 9, 2017Inventors: Mark Bradley Davis, Prashant R. Chandra
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Patent number: 9565132Abstract: Described are embodiments of methods, apparatuses, and systems for multi-protocol tunneling across a multi-protocol I/O interconnect of computer apparatus. A multi-protocol I/O interconnect may include a switching fabric operatively coupled to a first protocol-specific controller and a second protocol-specific controller, and may be configured to simultaneously route packets of the first protocol to the first protocol-specific controller and packets of the second protocol to the second protocol-specific controller. Other embodiments may be described and claimed.Type: GrantFiled: December 27, 2011Date of Patent: February 7, 2017Assignee: INTEL CORPORATIONInventors: Prashant R. Chandra, Kevin C. Kahn
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Patent number: 9430435Abstract: Described are embodiments of methods, apparatuses, and systems for multi-protocol tunneling across a multi-protocol I/O interconnect of computer apparatus. A method for multi-protocol tunneling may include establishing a first communication path between ports of a switching fabric of a multi-protocol interconnect of a computer apparatus in response to a peripheral device being connected to the computer apparatus, establishing a second communication path between the switching fabric and a protocol-specific controller, and routing, by the multi-protocol interconnect, packets of a protocol of the peripheral device from the peripheral device to the protocol-specific controller over the first and second communication paths. Other embodiments may be described and claimed.Type: GrantFiled: May 20, 2014Date of Patent: August 30, 2016Assignee: INTEL CORPORATIONInventors: Prashant R. Chandra, Kevin C. Kahn, Eran Galil, Efraim Kugman, Naama Zolotov, Vladimir Yudovich, Yoni Dishon, Elli Bagelman
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Patent number: 9304896Abstract: A data processing node has an inter-node messaging module including a plurality of sets of registers each defining an instance of a GET/PUT context and a plurality of data processing cores each coupled to the inter-node messaging module. Each one of the data processing cores includes a mapping function for mapping each one of a plurality of user level processes to a different one of the sets of registers and thereby to a respective GET/PUT context instance. Mapping each one of the user level processes to the different one of the sets of registers enables a particular one of the user level processes to utilize the respective GET/PUT context instance thereof for performing a GET/PUT action to a ring buffer of a different data processing node coupled to the data processing node through a fabric without involvement of an operating system of any one of the data processing cores.Type: GrantFiled: August 5, 2013Date of Patent: April 5, 2016Assignee: III Holdings 2, LLCInventors: Prashant R. Chandra, Thomas A. Volpe, Mark Bradley Davis, Niall Joseph Dalton
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Publication number: 20160077999Abstract: A data processing node has an inter-node messaging module including a plurality of sets of registers each defining an instance of a GET/PUT context and a plurality of data processing cores each coupled to the inter-node messaging module. Each one of the data processing cores includes a mapping function for mapping each one of a plurality of user level processes to a different one of the sets of registers and thereby to a respective GET/PUT context instance. Mapping each one of the user level processes to the different one of the sets of registers enables a particular one of the user level processes to utilize the respective GET/PUT context instance thereof for performing a GET/PUT action to a ring buffer of a different data processing node coupled to the data processing node through a fabric without involvement of an operating system of any one of the data processing cores.Type: ApplicationFiled: November 24, 2015Publication date: March 17, 2016Inventors: Prashant R. Chandra, Thomas A. Volpe, Mark Bradley Davis, Niall Joseph Dalton
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Patent number: 9256268Abstract: Methods and apparatus for implementing active interconnect link power management using an adaptive low-power link-state entry policy. The power state of an interconnect link or fabric is changed in response to applicable conditions determined by low-power link-state entry policy logic in view of runtime traffic on the interconnect link or fabric. The low-power link-state policy logic may be configured to include consideration of operating system input and Quality of Service (QoS) requirements for applications and devices employing the link or fabric, and device latency tolerance requirements.Type: GrantFiled: April 24, 2012Date of Patent: February 9, 2016Assignee: Intel CorporationInventors: Ren Wang, Ahmad Samih, Christian Maciocco, Tsung-Yuan Charlie Tai, James Jimbo Alexander, Prashant R. Chandra
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Patent number: 9164535Abstract: Described are embodiments of methods, apparatuses, and systems for time synchronization of a multi-protocol I/O interconnect of computer apparatus. A method for synchronizing time across the multi-protocol I/O interconnect may include providing a first local time of a first switch of a switching fabric of a multi-protocol interconnect to a second switch of the switching fabric, and adjusting a second local time of the second switch to the first local time. Other embodiments may be described and claimed.Type: GrantFiled: December 30, 2014Date of Patent: October 20, 2015Assignee: INTEL CORPORATIONInventors: Prashant R. Chandra, Vladimir Yudovich, Eran Galil, Efraim Kugman
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Patent number: 9141132Abstract: Described are embodiments of methods, apparatuses, and systems for time synchronization of a multi-protocol I/O interconnect of computer apparatus. A method for synchronizing time across the multi-protocol I/O interconnect may include providing a first local time of a first switch of a switching fabric of a multi-protocol interconnect to a second switch of the switching fabric, and adjusting a second local time of the second switch to the first local time. Other embodiments may be described and claimed.Type: GrantFiled: December 30, 2014Date of Patent: September 22, 2015Assignee: INTEL CORPORATIONInventors: Prashant R. Chandra, Vladimir Yudovich, Eran Galil, Efraim Kugman
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Patent number: 9047222Abstract: A device, method, and system are disclosed. In one embodiment the device includes a router to transmit data packets between multiple host controllers and one or more peripheral devices. The router can receive a data packet from a host controller and transmit the data packet to a peripheral device across a data transmission path. The peripheral device is coupled to the first data transmission path through a first universal multi-transport medium (UMTM) connector. The connector includes an optical coupling capable of transporting the first data packet within an optical signal and an electrical coupling capable of transporting the first data packet within an electrical signal.Type: GrantFiled: April 4, 2014Date of Patent: June 2, 2015Assignee: Intel CorporationInventors: Prashant R. Chandra, Ajay V. Bhatt, Kevin Kahn, Steven McGowan
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Publication number: 20150121115Abstract: Described are embodiments of methods, apparatuses, and systems for time synchronization of a multi-protocol I/O interconnect of computer apparatus. A method for synchronizing time across the multi-protocol I/O interconnect may include providing a first local time of a first switch of a switching fabric of a multi-protocol interconnect to a second switch of the switching fabric, and adjusting a second local time of the second switch to the first local time. Other embodiments may be described and claimed.Type: ApplicationFiled: December 30, 2014Publication date: April 30, 2015Inventors: Prashant R. Chandra, Vladimir Yudovich, Eran Galil, Efraim Kugman