Abstract: In one embodiment, the disclosure relates to a single flux quantum (SFQ) signal transmission line powered by an AC power source. The AC power source supplies power to a transformer having a primary winding and a secondary winding. The primary winding receives the AC signal and the secondary winding communicates the signal to the SFQ transmission line. The transmission line can optionally include an input filter circuit for receiving the incoming SFQ pulse. The filter circuit can have a resistor and an inductor connected in parallel. In an alternative arrangement, the filter circuit can comprise of an inductor. A first Josephson junction can be connected to the filter circuit and to the secondary winding. The Josephson junction triggers in response to the incoming SFQ pulse and regenerates a pulse signal in response to a power discharge from the secondary winding.

Abstract: In one embodiment, the disclosure relates to a single-flux quantum logic gate capable of providing output from one of the two inputs, which is also known as the A and NOT B gate. The logic gate includes a first input gate and a second input gate for respectively receiving a first input pulse and a second input pulse. An output gate is wired in parallel with the first input gate. A first Josephson junction and a second Josephson junction are connected to the first input gate and the second input gate, respectively. A cross-coupled transformer is also provided. The cross-coupled transformer diverts the first pulse from the output gate if the second pulse is detected at the second input gate. In an optional embodiment, the first Josephson junction has a first critical current which is selected to be less than the critical current of the second Josephson junction.

Abstract: In one embodiment, the disclosure relates to a single flux quantum (SFQ) signal transmission line powered by an AC power source. The AC power source supplies power to a transformer having a primary winding and a secondary winding. The primary winding receives the AC signal and the secondary winding communicates the signal to the SFQ transmission line. The transmission line can optionally include an input filter circuit for receiving the incoming SFQ pulse. The filter circuit can have a resistor and an inductor connected in parallel. In an alternative arrangement, the filter circuit can comprise of an inductor. A first Josephson junction can be connected to the filter circuit and to the secondary winding. The Josephson junction triggers in response to the incoming SFQ pulse and regenerates a pulse signal in response to a power discharge from the secondary winding.

Abstract: In one embodiment, the disclosure relates to a single flux quantum (SFQ) signal transmission line powered by an AC power source. The AC power source supplies power to a transformer having a primary winding and a secondary winding. The primary winding receives the AC signal and the secondary winding communicates the signal to the SFQ transmission line. The transmission line can optionally include an input filter circuit for receiving the incoming SFQ pulse. The filter circuit can have a resistor and an inductor connected in parallel. In an alternative arrangement, the filter circuit can comprise of an inductor. A first Josephson junction can be connected to the filter circuit and to the secondary winding. The Josephson junction triggers in response to the incoming SFQ pulse and regenerates a pulse signal in response to a power discharge from the secondary winding.

Abstract: The disclosure relates to a method for providing a logic circuit element. The method includes arranging a series of Josephson junctions between a first Josephson junction and a second Josephson junction, the first Josephson junction having a first critical current (Ic1) and the second Josephson junction having a second critical current (Ic2); providing a working current to the first Josephson junction, the working current transmitting to the second Josephson junction through the series of the Josephson junctions; wherein the working current is sufficiently high to trigger the second Josephson junction while sufficiently low to not disturb super-conductivity of the series of intermediate Josephson junctions.

Abstract: Superconducting single flux quantum circuits are disclosed herein, each having at least one Josephson junction which will flip when the current through it exceeds a critical current. Bias current for the Josephson junction is provided by a biasing transformer instead of a resistor. The lack of any bias resistors ensures that unwanted power dissipation is eliminated.

Abstract: Superconducting single flux quantum circuits are disclosed herein, each having at least one Josephson junction which will flip when the current through it exceeds a critical current. Bias current for the Josephson junction is provided by a biasing transformer instead of a resistor. The lack of any bias resistors ensures that unwanted power dissipation is eliminated.

Abstract: In one embodiment, the disclosure relates to a single flux quantum (SFQ) signal transmission line powered by an AC power source. The AC power source supplies power to a transformer having a primary winding and a secondary winding. The primary winding receives the AC signal and the secondary winding communicates the signal to the SFQ transmission line. The transmission line can optionally include an input filter circuit for receiving the incoming SFQ pulse. The filter circuit can have a resistor and an inductor connected in parallel. In an alternative arrangement, the filter circuit can comprise of an inductor. A first Josephson junction can be connected to the filter circuit and to the secondary winding. The Josephson junction triggers in response to the incoming SFQ pulse and regenerates a pulse signal in response to a power discharge from the secondary winding.

Abstract: The disclosure generally relates to a method and apparatus for providing high-speed, low signal power amplification. In an exemplary embodiment, the disclosure relates to a method for providing a wideband amplification of a signal by forming a first transmission line in parallel with a second transmission line, each of the first transmission line and the second transmission line having a plurality of superconducting transmission elements, each transmission line having a transmission line delay; interposing a plurality of amplification stages between the first transmission line and the second transmission line, each amplification stage having an resonant circuit with a resonant circuit delay; and substantially matching the resonant circuit delay for at least one of the plurality of amplification stages with the transmission line delay of at least one of the superconducting transmission lines.

Abstract: A second order superconductor delta-sigma analog-to-digital modulator having an input for receiving an analog signal, a first integrator coupled to the input, a second integrator cascaded with the first integrator, and a quantum comparator digitizing output from the second integrator reduces quantization noise by providing matched quantum accurate DACs in a feedback loop between output from the quantum comparator and input to the first integrator. The matched quantum accurate feedback DACs produce identically repeatable voltage pulses, may be configured for multi-bit output, may be time-interleaved to permit higher clocking rates, and may be employed in a balanced bipolar configuration to allow inductive input coupling. Bipolar feedback is balanced when gain of a first DAC exceeds gain of a matched, opposite polarity DAC by the amount of implicit feedback from the comparator into the second integrator.

Abstract: The disclosure relates to a method for providing a logic circuit element. The method includes arranging a series of Josephson junctions between a first Josephson junction and a second Josephson junction, the first Josephson junction having a first critical current (Ic1) and the second Josephson junction having a second critical current (Ic2); providing a working current to the first Josephson junction, the working current transmitting to the second Josephson junction through the series of the Josephson junctions; wherein the working current is sufficiently high to trigger the second Josephson junction while sufficiently low to not disturb super-conductivity of the series of intermediate Josephson junctions.

Abstract: Superconducting single flux quantum circuits are disclosed herein, each having at least one Josephson junction which will flip when the current through it exceeds a critical current. Bias current for the Josephson junction is provided by a biasing transformer instead of a resistor. The lack of any bias resistors ensures that unwanted power dissipation is eliminated.

Abstract: A clock recovery circuit (10) for a superconductor system that enables the phase of a system clock to be instantaneously reset without any pulse interaction. The clock recovery circuit (10) includes a Josephson transmission line oscillator loop (14) of length 2T, where T is equal to one clock period. First and second data inputs (16, 18) are for injecting a data pulse onto the oscillator loop (14). A pulse generator (24) is for injecting an initial clock pulse onto the oscillator loop (14) that is output as periodic clock signals. An output tap (12) is for outputting the data pulse from one of the first and second data inputs (16, 18), and the periodic clock signals in the absence of the data pulse. When the data pulse is input on one of first and second output taps (32, 34), the clock phase is instantaneously reset.

Abstract: A single flux quantum (SFQ) pulse is generated (502) by injecting a superconductor output signal as a first signal at a “start” input (108) coupled to a superconductor delay element (104). The SFQ pulse is reflected (504) back and forth between first and second superconductor reflectors (102, 106) coupled to opposite ends of the superconductor delay element, thereby generating a time-disperse plurality of SFQ pulses at an output (110) coupled to the superconductor delay element. Thereafter, a second signal is input at a “stop” input (112) coupled to one of the first and second superconductor reflectors, thereby interrupting (506) the reflecting of the SFQ pulse at the one of the first and second superconductor reflectors, thus ending the generating of the time-disperse plurality of SFQ pulses at the output.

Abstract: A digital first-in first-out (FIFO) buffer (10) for use with Single Flux Quantum (SFQ) superconductive integrated circuits. The digital FIFO buffer (10) includes a clock-storage circuit (14) for receiving and storing load and read clock signals (100, 104) and a data-storage circuit (16) connected to the clock-storage circuit (14) for receiving and storing data signal pulses (102) in the order which the data signal pulses (102) are received relative to the load clock signal (100). The data-storage circuit (16) outputs the SFQ pulse signal independent of the load clock signal (100). The previously stored clock and data signal pulses (100, 102) provide physical back pressure to their subsequent signal pulses.

Abstract: A crossbar switch includes a cross-point matrix with n input rows of cross-points and m output columns of cross-points. The crossbar switch further includes n decoders connected to the n input rows. Each of the n rows includes a single serial address input, a shift input and a data input. A serial address and data enter the address input and the data input in parallel. A shift sequence is transmitted on the single shift input. The data flows before the shift sequence on the shift input is complete. The data is shifted through the crossbar switch using a clock that is generated on-chip using a clock recovery circuit. The decoder converts a binary address input into a serial address and includes an N-bit counter with a plurality of toggle flip-flops. The crossbar switch is implemented using superconductor digital electronics such as rapid single flux quantum (RSFQ) logic.

Abstract: A superconductor memory array (10) has a high associated throughput with low power dissipation and a simple architecture. The superconductor memory array (10) includes memory cells (12a-12d) arranged in a row-column format and each including a storage loop (14a-14d) with a Josephson junction (16a-16d) for storing a binary value. Row address lines (24a, 24b) each are magnetically coupled in series to a row of the memory cells (12a-12d), and column address lines (26a, 26b) each are connected in series to a column of the memory cells (12a-12d). A sense amplifier (38a, 38b) is located on each of the column address lines (26a, 26b) for sensing state changes in the memory cells (12a-12d) located in the columns during a READ operation initiated by row address line READ signals.

Abstract: A superconductor memory array (10) has a high associated throughput with low power dissipation and a simple architecture. The superconductor memory array (10) includes memory cells (12a-12d) arranged in a row-column format and each including a storage loop (14a-14d) with a Josephson junction (16a-16d) for storing a binary value. Row address lines (24a, 24b) each are magnetically coupled in series to a row of the memory cells (12a-12d), and column address lines (26a, 26b) each are connected in series to a column of the memory cells (12a-12d). A sense amplifier (38a, 38b) is located on each of the column address lines (26a, 26b) for sensing state changes in the memory cells (12a-12d) located in the columns during a READ operation initiated by row address line READ signals.

Abstract: A single flux quantum (SFQ) pulse is generated (502) by injecting a superconductor output signal as a first signal at a “start” input (108) coupled to a superconductor delay element (104). The SFQ pulse is reflected (504) back and forth between first and second superconductor reflectors (102, 106) coupled to opposite ends of the superconductor delay element, thereby generating a time-disperse plurality of SFQ pulses at an output (110) coupled to the superconductor delay element. Thereafter, a second signal is input at a “stop” input (112) coupled to one of the first and second superconductor reflectors, thereby interrupting (506) the reflecting of the SFQ pulse at the one of the first and second superconductor reflectors, thus ending the generating of the time-disperse plurality of SFQ pulses at the output.

Abstract: The self inductance associated with a capacitance A52 in a superconductor integrated circuit (FIG. 1) is reduced by adding a layer of superconductor metal (A54) overlying the capacitor, effectively producing a negative inductance to counteract the self-inductance of the capacitor leads, thereby reducing inductance of the circuit. As a result it possible to transfer a single flux quantum (“SFQ”) pulse through the capacitor. Capacitors (19 and 25 FIG. 5) of the foregoing type are incorporated in superconductor integrated circuit SFQ transmission lines (FIG. 5) to permit SQUID-to-SQUID transfer of SFQ pulses, while maintaining the circuit grounds of the respective SQUIDs in DC isolation. Bias current (10) may be supplied to multiple SQUIDs (1 & 3, 7 & 9 FIG. 5) serially, reducing the supply current required previously for operation of multiple SQUIDs.