Abstract: Novel shielded flat wire pair and cable implement flat, smooth conductors coated with insulation bonded together, providing rectangular cross-sections and equidistant, smooth surfaces for high frequency signal current flow. Flat wire pairs with conductive covers and symmetrically placed shield conductors in grooves between flat wires minimize intra-pair signal flow skew. Shielded flat wire pairs are placed within a cable assembly with adjacent wire pairs oriented orthogonally, minimizing crosstalk and rendering crosstalk common-mode. Such orientation of flat wire pairs is assisted by an internal separator, which may be electrically conductive and grounded providing enhanced pair to pair isolation. Presence of flat wire pairs and an internal separator in a cable positions additional single wires in the cable firmly against a grounded external shield, ensuring a predetermined impedance for these signal wires.

Abstract: Novel shielded flat wire pair and cable implement flat, smooth conductors coated with insulation bonded together, providing rectangular cross-sections and equidistant, smooth surfaces for high frequency signal current flow. Flat wire pairs with conductive covers and symmetrically placed shield conductors in grooves between flat wires minimize intra-pair signal flow skew. Shielded flat wire pairs are placed within a cable assembly with adjacent wire pairs oriented orthogonally, minimizing crosstalk and rendering crosstalk common-mode. Such orientation of flat wire pairs is assisted by an internal separator, which may be electrically conductive and grounded providing enhanced pair to pair isolation. Presence of flat wire pairs and an internal separator in a cable positions additional single wires in the cable firmly against a grounded external shield, ensuring a predetermined impedance for these signal wires.

Abstract: An inductor structure comprised of a magnetic section and a single turn solenoid. The single turn solenoid to contain within a portion of the magnetic section and circumscribed by the magnetic section.

Abstract: A novel varied twist-rate wire pair and cable architecture are disclosed. The invention implements variable twist rate along twisted wire pair length, providing approximately equivalent physical and electrical length values for segments of such twisted wire pair, and consequently, low delay skew, and substantially minimized inter-pair crosstalk due to reduction of twist-rate correlation along the length of a UTP cable employing the invention. Due to the elimination of the need for shielding, the invention method yields flexible, low-cost cables that may be employed for extremely high data throughput applications such as HDMI. Minimized inter-pair skew also eliminates the need for channel re-alignment at the end of long cable runs. Through these benefits, the invention twisted pair and cable facilitates continued enhancements in multi-media electronics while containing cost for high-performance interconnect.

Abstract: A novel flat-wire-pair and cable architecture are disclosed. The invention implements flattened conducting wires coated with insulation that are bonded to each other, providing approximately rectangular cross-sections and flat surfaces for the transport of charge through the wires. Flat wire pairs are then placed within a cable assembly such that adjacent wire pairs are oriented orthogonally or in other such manner adjacent to each other to minimize crosstalk and render crosstalk common-mode. Flat wire pairs are also shielded for additional cross-talk minimization as well as near-field EMI minimization. A cable consisting of multiple flat wire pairs may also be shielded in its external jacket that maintains cable structure, and may include additional conductors for reference and static signals. Through these enhancements, the invention cable architecture eliminates intra-pair and inter-pair skew while substantially reducing signal loss due to skin-effect as well as rendering crosstalk harmless.

Abstract: A device comprises a substrate core having power paths through it and an input/output signal routing layer upon the core substrate. An integrated circuit may be arranged on the routing layer such that the integrated circuit is electrically coupled to the substrate core through the routing layer.

Abstract: A novel flat-wire-pair cable and resonant filter termination employing active interconnect principles is disclosed. The invention implements flattened conducting wires coated with insulation that are bonded to each other, providing approximately rectangular cross-sections and flat surfaces for the transport of charge through the wires. The flat wire pair may then be twisted for additional cross-talk minimization, with the twist occurring simultaneously and in identical fashion on both wires due to their attached arrangement. The terminating ends of the cable are routed on an insulating substrate forming a connector body, with the traces ending in conducting structures providing a matched resonating filter function. This filter is tuned to provide maximal benefit for the highest significant spectral content in transmitted signals. Through these enhancements, the invention interconnect architecture substantially reduces signal loss due to skin-effect and eliminates intra-pair skew.

Abstract: A novel flat-wire-pair and cable architecture are disclosed. The invention implements flattened conducting wires coated with insulation that are bonded to each other, providing approximately rectangular cross-sections and flat surfaces for the transport of charge through the wires. Flat wire pairs are then placed within a cable assembly such that adjacent wire pairs are oriented orthogonally or in other such manner adjacent to each other to minimize crosstalk and render crosstalk common-mode. Flat wire pairs are also shielded for additional cross-talk minimization as well as near-field EMI minimization. A cable consisting of multiple flat wire pairs may also be shielded in its external jacket that maintains cable structure, and may include additional conductors for reference and static signals. Through these enhancements, the invention cable architecture eliminates intra-pair and inter-pair skew while substantially reducing signal loss due to skin-effect as well as rendering crosstalk harmless.

Abstract: The invention proposes noise suppression circuits that are assembled together with capacitors on a CPU package. Charge is conveyed from the capacitors dedicated to the active noise suppression function through electrical circuit pathways such as controlled electronic switches integrated into a semiconductor substrate. These circuit pathways connect to the capacitor terminals through the package of the active noise suppression semiconductor chip. The circuits within the active device may be any combination of semiconductor switches and/or voltage regulators, and may also contain voltage and current sensing circuitry. The charge transfer switches are designed with control circuitry that dynamically modulate the turn-on threshold voltage of the switches and maintain the switches at an operating point very close to actual turn-on. These enhancements ensure very fast turn-on action for the switches improving voltage droop suppression capability.

Abstract: A novel source-coupled differential driver circuit fully compatible with digital visual interface TMDS signaling specification is disclosed. Driven output signals are connected to the source terminals of driving switches in the invention circuit, minimizing the detrimental impact of miller coupling capacitance between gate nodes and driven output nodes upon output slew-rate, enabling higher frequencies of operation. Output signal undershoots and overshoots are also mitigated by the invention driver circuit due in part to the in-phase relationship of the gate node to the driven output node of a driver switch. Overall link performance is significantly enhanced by this SCDL driver architecture due to improved slew rates and signal integrity.

Abstract: A novel source-coupled differential driver circuit fully compatible with digital visual interface (DVI/HDMI) signaling specification is disclosed. Driven output signals are connected to the source terminals of driving switches in the invention circuit, minimizing the detrimental impact of miller coupling capacitance between gate nodes and driven output nodes upon output slew-rate, enabling higher frequencies of operation. Undriven output wires are connected to source-termination impedances, providing a matched return current to the driven current signal, and reducing return path impedance substantially. Matched differential current drive from the source ensures true-differential signaling, eliminating shield current flow and improving signal integrity. Bit error rate (BER) is reduced and overall link performance is significantly enhanced due to improved slew rates, true-differential signaling and greater signal integrity, enabling long reach and high-speed, high-definition multi-media data transmission.

Abstract: A novel wideband, low bit-error rate, dual-loop data recovery architecture is disclosed. The architecture employs a wideband clock receiver PLL that receives a synchronizing clock and generates the necessary high frequency clock for data transmission and recovery. The wideband PLL translates operating frequency information into a current reference that is transmitted to all data receiver channels. This current reference is employed to control a matched open-loop delay line at each data receiver. The phase clocks generated by this matched delay line maintain their angular relationship with respect to the primary clock transmitted by the wideband PLL over the entire range of frequencies. A bang-bang algorithm employed in the data receivers renders any delay mismatch between data receiver delay lines and the primary PLL inconsequential.

Abstract: A noise-minimizing supply regulation architecture enabling high-performance integrated mixed-signal circuit systems is disclosed. The architecture identifies noise-generating and noise-sensitive sub-components of a PLL or other complex mixed-signal circuit and isolates the noise-sensitive sub-components from the noise-generating sub-components through the use of separate, wideband, high-PSRR voltage regulators for the two isolated supply domains. This isolation is further enhanced through techniques that separate or isolate the substrate regions occupied by the two types of sub-components. Further, internally generated noise is minimized by the allocation of available decoupling capacitance area in proportion to the noise generated within the domains. This supply isolation architecture achieves very low noise operation of the critical components of the mixed-signal integrated circuit system, thereby improving output quality.

Abstract: A novel wideband, low bit-error rate, dual-loop data recovery architecture is disclosed. The architecture employs a wideband clock receiver PLL that receives a synchronizing clock and generates the necessary high frequency clock for data transmission and recovery. The wideband PLL translates operating frequency information into a current reference that is transmitted to all data receiver channels. This current reference is employed to control a matched open-loop delay line at each data receiver. The phase clocks generated by this matched delay line maintain their angular relationship with respect to the primary clock transmitted by the wideband PLL over the entire range of frequencies. A bang-bang algorithm employed in the data receivers renders any delay mismatch between data receiver delay lines and the primary PLL inconsequential.

Abstract: A novel push-pull differential signaling circuit architecture exceptionally suited for 2-wire transceiver implementations is disclosed. The invention Class-B differential signaling (CBDS) architecture fully utilizes equivalent current sources connecting from the positive power rail and to the negative power rail to generate a ‘true-differential’ signal in a differential interconnect pair. By adopting a ‘Class B’ or push-pull drive structure, the invention architecture maximizes power efficiency, improving upon traditional differential signaling implementations by a factor of 2 or more. A novel combination of a bias circuit and the Class B output drive circuit ensures that the push and pull currents are very closely matched over fabrication process, voltage and temperature. The current mode operation and bi-lateral nature of the output driver ensures that there are no current spikes in the power supply connecting to the invention circuits, thereby minimizing on-chip decoupling capacitance requirements.

Abstract: The invention proposes an interposer assembly architecture for noise suppression circuits on the package of a CPU or high power, high frequency VLSI device. In this architecture, charge is stored on dedicated capacitors at a voltage substantially higher than the operating voltage of the VLSI device. These capacitors are mounted upon active circuits that are packaged to match the size and form factor of the capacitors and this assembly is then attached to the package substrate. Charge is conveyed from the capacitor terminals on the backside of the packaged active circuits chip. Depending upon the capacitor construction, these terminals may either be double-sided contact terminals along the edge of the active device's package, or may be feed-through contacts.

Abstract: An inductor structure comprised of a magnetic section and a single turn solenoid The single turn solenoid to contain within a portion of the magnetic section and circumscribed by the magnetic section.

Abstract: An adaptable, low-power drive circuit for transistor switches requiring control input current is disclosed. In one embodiment of the invention, a current source output replaces the prior art voltage drive circuits and associated external current-limiting resistor. The current-source drive circuit provides both a high impedance as well as variability. The high impedance of the current-source drive circuit enables a reduction in the value of the resistance-bypass capacitor employed in the prior art. The variability in the output current provided by the current-source circuit allows the drive circuits to optimize the control current flowing into the switch device as the characteristics of the switch device change with operating temperature. The drive circuit is capable of providing as output either a desired current, at a high output impedance, or a desired voltage, at a low output impedance, employing a shared amplifier and output transistor.

Abstract: The invention proposes noise suppression circuits mounted on the package of a high power, high frequency ULSI component. In this architecture, termed an active noise regulator (ANR), charge is stored on dedicated reservoir capacitors at a voltage substantially higher than the operating voltage of the ULSI device. These reservoir capacitors are mounted upon active circuits packaged to match the size and form factor of the capacitors and this assembly is then attached to the package substrate. Charge is conveyed from the reservoir capacitors to the ULSI power grid when there is a sudden load current demand in the ULSI device. The capacitors are depleted by the flow of charge through inductances in the discharge pathway. The capacitors are then recharged either by the overshoot that results from a sudden release of the ULSI load current demand or by a gated charging pathway connected to a high voltage supply.

Abstract: A high capacitance substrate. The substrate includes a core tolerant to sintering thereon of a high k material to provide increased capacitance. The core may be non-ceramic. The material sintered thereon may have a dielectric constant in excess of about 4. The substrate may be a package substrate electrically coupled to a die.