Abstract: A high capacitance substrate. The substrate includes a core tolerant to sintering thereon of a high k material to provide increased capacitance. The core may be non-ceramic. The material sintered thereon may have a dielectric constant in excess of about 4. The substrate may be a package substrate electrically coupled to a die.

Abstract: A ferroelectric memory device and method for reading such a device utilize capacitive coupling between a bit line and sense amplifier. The gain depends on a capacitance ratio rather than the absolute value of a capacitor. Ratiometric gain control reduces the gain variability of a sense amplifier, thereby allowing more accurate sensing. Attenuating the signal from an active bit line eliminates the need for high voltage devices in a sense amplifier arrangement.

Abstract: A voltage dependent capacitor to provide soft error rate tolerance in an integrated circuit is disclosed. In one embodiment, a parallel n-p voltage dependent capacitor is used to protect a node from noise. In another embodiment, an nFET-in-nWell voltage dependent capacitor is used to provide a soft error rate tolerant capacitor with reduced area.

Abstract: Electronic devices having voltage variable capacitances are formed using CMOS fabrication processes. The devices are capable of decreasing noise of one polarity and amplifying noise of the opposite polarity. For one embodiment, a transistor having a gate oxide layer is operated in the depletion region to form a capacitive device. In an alternate embodiment, a CMOS transistor having an n-type substrate, all p-type polysilicon gate, an n-type source and drain, and a gate oxide layer is operated in the depletion region to form a capacitive device. For one embodiment, the disclosed devices are used in circuits for decoupling multiple voltage power supplies. In an alternate embodiment, the devices are used in circuits for damping power supply grid network resonances. In still another alternate embodiment, the devices are used in circuits for decoupling noise in power supply signals operating at low voltages.

Abstract: A differential amplifier has input and output terminals to generate a second signal at the output terminals for a first signal. The amplifier has feedback switches between the output terminals and the input terminals. Offset capacitors are coupled to the differential amplifier at the input terminals and reference voltages via charging switches to provide offsets for the first signal form the reference voltages via input switches.

Abstract: A ferroelectric memory device and method for reading such a device utilize capacitive coupling between a reference circuit and a sense amplifier. The amount of sneak charge canceled from a data bit line depends on the relative capacitances of a coupling capacitor and another capacitor used to integrate sneak charge from a reference bit line. The use of linear-responding components improves stability.

Abstract: A ferroelectric memory device and method for reading such a device utilize an AC excitation on an active bit line to cancel sneak currents during a read operation. A memory device comprises an active ferroelectric cell disposed between an active word line and an active bit line, and a passive ferroelectric cell disposed between a passive word line and the active bit line. Peripheral circuitry is adapted to drive the active word line with active word line biasing, the passive word line with passive word line biasing, and the active bit line with an AC excitation during a read operation.

Abstract: A ferroelectric memory device and method for reading such a device utilize capacitive coupling between a bit line and sense amplifier. The gain depends on a capacitance ratio rather than the absolute value of a capacitor. Ratiometric gain control reduces the gain variability of a sense amplifier, thereby allowing more accurate sensing. Attenuating the signal from an active bit line eliminates the need for high voltage devices in a sense amplifier arrangement.

Abstract: A ferroelectric memory device and method for reading such a device utilize an AC excitation on an active bit line to cancel sneak currents during a read operation. A memory device comprises an active ferroelectric cell disposed between an active word line and an active bit line, and a passive ferroelectric cell disposed between a passive word line and the active bit line. Peripheral circuitry is adapted to drive the active word line with active word line biasing, the passive word line with passive word line biasing, and the active bit line with an AC excitation during a read operation.

Abstract: A voltage-to-current circuit utilizes an NMOS-input voltage-to-current (V-I) converter and a PMOS-input V-I converter, with both driving a common gate output stage. Each of the V-I converters includes a transconductance amplifier and a current mirror. The common gate output stage includes two series connected complementary pairs of transistors. One complementary pair drives the output, and the other complementary pair biases the first. The V-I circuit can be utilized as part of a phase detector, which is in turn can be utilized as part of a phase lock loop or a delay lock loop.

Abstract: A state of a memory element in a memory device is accessed by conditioning a number of wordlines and an addressed one of a number of bitlines in the memory device. This causes an addressed one of the memory elements in the device to release a signal charge and an unaddressed one to release a sneak charge into the addressed bitline. This charge release causes the current in the addressed bitline to increase. This current is integrated, and integration is halted when a signal to sneak ratio of the addressed bitline is maximized. The integration yields a total bitline charge value that may be used to obtain a more accurate measurement of the released signal charge.

Abstract: In some embodiments, the invention involves a die having a first conductor carrying a power supply voltage and a second conductor carrying a ground voltage. A semiconductor capacitor operating in depletion mode is coupled between the first and second conductors to provide decoupling capacitance between the first and second conductors, the semiconductor capacitor having a gate voltage. Various configurations may be used including: n+ gate poly and n+ source/drain regions in an n−body; p+ gate poly and n+ source/drain regions in an n-body; p+ gate poly and p+ source/drain regions in an n-body; p+ gate poly and p+ source/drain regions in a p-body; n+ gate poly and p+ source/drain regions in a p-body; n+ gate poly and n+ source/drain regions in a p-body. The power supply voltage may have a larger absolute value than does a flatband voltage.

Abstract: A state of a memory element in a memory device is accessed by conditioning a number of wordlines and an addressed one of a number of bitlines in the memory device. This causes an addressed one of the memory elements in the device to release a signal charge and an unaddressed one to release a sneak charge into the addressed bitline. This charge release causes the current in the addressed bitline to increase. This current is integrated, and integration is halted when a signal to sneak ratio of the addressed bitline is maximized. The integration yields a total bitline charge value that may be used to obtain a more accurate measurement of the released signal charge.

Abstract: An output circuit generates an output signal. The output signal has a duty cycle from an input signal. A level extractor couple to the output circuit to extract a direct current (DC) level from the output signal. The DC level is a representative of the duty cycle. An integrator couple to the level extractor to integrate the DC level. The integrator generates a current control signal to adjust the duty cycle.

Abstract: A low jitter external clocking system and method are disclosed. According to one embodiment of the present invention, a differential clock signal is received on a first clock signal line and a second clock signal line. A differential amplifier coupled to the first clock signal line and the second clock signal line amplifies the differential clock signal into a single-ended output clock signal.

Abstract: An adaptive body bias circuit forward or reverse biases bodies of transistors within a compensated circuit as a result of measured parameters of an integrated circuit. The adaptive body bias circuit includes a matched circuit that includes a replica of a signal path within the compensated circuit. The phase of a clock signal at the input to the matched circuit is compared to a phase of a delayed clock signal at the output of the matched circuit. When the delay through the matched circuit varies about one period of the clock signal, a non-zero error value is produced. A bias voltage is generated as a function of the error value, and the bias voltage is applied to the compensated circuit as well as the matched circuit. Integrated circuits can include many adaptive body bias circuits. Bias values can be stored in memories for later use, and bias values within memories can be updated periodically to compensate the circuit over time.

Abstract: A voltage-to-current circuit utilizes an NMOS-input voltage-to-current (V-I) converter and a PMOS-input V-I converter, with both driving a common gate output stage. Each of the V-I converters includes a transconductance amplifier and a current mirror. The common gate output stage includes two series connected complementary pairs of transistors. One complementary pair drives the output, and the other complementary pair biases the first. The V-I circuit can be utilized as part of a phase detector, which is in turn can be utilized as part of a phase lock loop or a delay lock loop.

Abstract: An output circuit generates an output signal. The output signal has a duty cycle from an input signal. A level extractor couple to the output circuit to extract a direct current (DC) level from the output signal. The DC level is a representative of the duty cycle. An integrator couple to the level extractor to integrate the DC level. The integrator generates a current control signal to adjust the duty cycle.

Abstract: A method including sensing a duty cycle, measuring the variation of the duty cycle from a desired duty cycle, and differentially adjusting the rising and falling edges of the duty cycle is disclosed.

Abstract: A differential amplifier has input and output terminals to generate a second signal at the output terminals for a first signal. The amplifier has feedback switches between the output terminals and the input terminals. Offset capacitors are coupled to the differential amplifier at the input terminals and reference voltages via charging switches to provide offsets for the first signal form the reference voltages via input switches.