Abstract: Isocyanates are produced in the gas phase and by-products such as ammonium halides are selectively separated from the gas phase by desublimation.

Abstract: A FET gas sensor having a relatively low operating temperature, for example, room temperature, is free from cross sensitivities from interfering gases by a preceding in-line filter. The sensor's service life is substantially stabilizable by using fabric-like activated charcoal filters which can be regenerated by a moderate temperature increase, and by limiting the diffusion of the analyte gas, which is made possible by the relatively small amount of gas detectable on the sensitive layer of the sensor. This substantially increases the service life of the filters. The gas sensor eliminates cross sensitivities to thereby increase the detection reliability thereof. Also, the gas sensor has relative long term stability and is economical to build. The gas sensor can read relatively weak signals generated by gas-sensitive layers, for example, without other stronger gas signals interfering with the weak signals.

Abstract: The invention starts from a known component of quartz glass for use in semiconductor manufacture, which component at least in a near-surface region shows a co-doping of a first dopant and of a second oxidic dopant, said second dopant containing one or more rare-earth metals in a concentration of 0.1-3% by wt. each (based on the total mass of SiO2 and dopant). Starting from this, to provide a quartz glass component for use in semiconductor manufacture in an environment with etching action, which component is distinguished by both high purity and high resistance to dry etching and avoids known drawbacks caused by co-doping with aluminum oxide, it is suggested according to the invention that the first dopant should be nitrogen and that the mean content of metastable hydroxyl groups of the quartz glass is less than 30 wtppm.

Abstract: A reactor (10) for anaerobic waste water treatment is designed as a loop-type column reactor comprising a central flow channel (20). In the annular space (40) between the central flow channel (20) and the reactor wall, there are positioned carrier elements (50) for immobilizing microorganisms, with flow passages being provided between adjacent carrier elements (50). The lower portion of the reactor (30), below the carrier elements, is designed as a space intended to receive waste water having microorganisms floating therein during operation of the reactor (10). During operation, there are provided both floating microorganisms and microorganisms that are immobilized on the carrier elements. The waste water to be treated flows centrally downward and up again along the carrier elements (40), with the flow being generated in part by the gas development of the microorganisms.

Abstract: A gas-sensitive field-effect transistor may be formed from a substrate with a gas-sensitive layer and a transistor processed separately and then assembled. The substrate may be patterned to form spacers by which the height of an air gap between the transistor and the sensitive layer may be adjustable to a relatively precise degree. Formation of the spacers can be achieved by patterning the substrate using material-removal techniques. The height of the spacers may be adjusted in the layer thickness of the gas-sensitive layer and for the transistor fabricated using a CMOS process. Suitable techniques for producing recesses between the spacers include, for example, polishing, cutting, sandblasting, lithographic dry etching, or wet-chemical etching. Suitable materials for the substrate may include, for example, glass, ceramic, aluminum oxide, silicon, or a dimensionally stable polymer.

Abstract: In a method for initializing at least one electronic circuit unit of an electric circuit, a supply voltage is applied to a power supply connection unit of the electronic circuit in order to supply electrical power to the electronic circuit unit. A reference signal is applied to the electronic circuit unit via a reference signal connection unit. A blocking unit connected to the reference signal connection unit blocks the electronic circuit unit until the reference signal is supplied. An input signal to the electronic circuit unit is supplied via an input signal connection unit of the electronic circuit and an output signal is output by an output signal connection unit of the electronic circuit. The output signal is dependent on the input signal and the reference signal supplied to the electronic circuit unit.

Abstract: A field effect semiconductor comprises a semiconductor layer having a surface, a first and a second semiconductor region in the semiconductor layer, which are arranged next to one another at the surface of the semiconductor layer, an insulating layer between the first semiconductor region and the second semiconductor region, a semiconductor strip on the surface of the semiconductor layer, which semiconductor strip overlaps the first semiconductor region and the second semiconductor region and adjoins these. A gate overlaps the semiconductor strip at least in the region of the insulating layer. A gate dielectric insulates the gate from the semiconductor strip the first semiconductor region and the second semiconductor region. The semiconductor strip and the gate being formed such that the semiconductor strip is electrically insulating at a first predetermined gate voltage and is electrically conductive at a second predetermined gate voltagero.

Abstract: The invention relates to a method for preparing metallic workpieces for cold forming by contacting the metallic surfaces thereof with an aqueous acid phosphating solution so as to embody at least one phosphate coating and then coating the phosphate-coated surfaces with at least one lubricant in order to embody at least one lubricant layer. According to the inventive method, the phosphating solution essentially contains only calcium, magnesium, or/and manganese as cations that are selected among cations of main group 2 and subgroups 1, 2, and 5 to 8 of the periodic table of chemical elements in addition to phosphate. Furthermore, an alkaline earth metal-containing phosphating solution is free from fluoride and complex fluoride while the phosphating process is carried out electrolytically. The invention further relates to a metallic workpiece that is coated accordingly as well as the use of workpieces coated in said manner.

Abstract: A semiconductor memory device with redundant memory cells and a method for operating a semiconductor memory device is disclosed. One embodiment provides at least one memory cell and at least one redundant memory cell. The method includes reading out data written in the memory cell; determining whether the read-out data concur with target data; reprogramming or reconfiguring, respectively, the semiconductor device, so that the redundant memory cell replaces the memory cell if the read-out data do not concur with the target data; and writing the target data in the redundant memory cell already during the reprogramming or reconfiguring, respectively.

Abstract: An integrated circuit includes a current generator circuit with a first input terminal for applying a reference voltage and a second input terminal for applying an input voltage, which is generated internally from an externally applied supply voltage by a voltage generator circuit. The current generator circuit is connected to an output terminal via an interconnect. A first current flows on the interconnect in a test operating state of the integrated circuit. The current generator circuit generates a first partial current in a first test cycle of a test operating state and a second partial current in a subsequent second test cycle. The partial currents are each superposed on the first current on the interconnect. Consequently, three currents occur at the output terminal during the test operating state. The internally generated input voltage of the current generator circuit is determined from the three currents and the reference voltage.

Abstract: An interface between a test access port of an integrated circuit chip and a test equipment, which is designed to perform a functional test of the chip, is provided. The interface includes electric pads on either sides of the chip and the test equipment. The pads are arranged to interact by means of capacitive coupling, when a test data signal is input to one of the pads. Preferably, both pads are connected with either a receiver or a driver depending on the direction of the data flow. The electric pads relating to the chip's side may be arranged within the wiring substrate of a chip package, particularly along edge portion of the substrate, which encompasses an inner portion of the substrate, in which a ball-grid-array can be formed.

Abstract: A reactor (10) for anaerobic waste water treatment is designed as a loop-type column reactor comprising a central flow channel (20). In the annular space (40) between the central flow channel (20) and the reactor wall, there are positioned carrier elements (50) for immobilizing microorganisms, with flow passages being provided between adjacent carrier elements (50). The lower portion of the reactor (30), below the carrier elements, is designed as a space intended to receive waste water having microorganisms floating therein during operation of the reactor (10). During operation, there are provided both floating microorganisms and microorganisms that are immobilized on the carrier elements. The waste water to be treated flows centrally downward and up again along the carrier elements (40), with the flow being generated in part by the gas development of the microorganisms.

Abstract: A system and method for testing a memory device is disclosed. One embodiment includes a plurality of memory cells. Each of the memory cells can be controlled by an address. A test memory for storing test results is provided. An address comparing unit is configured to determine whether the address of a memory cell lies in a predetermined address space. A controllable unit for storing test results is connected with the test memory and the address comparing unit. The controllable unit is controlled by the address comparing unit such that error information of the tested memory cell is only stored in the test memory if the address of the tested memory cell lies in the selected address space.

Abstract: The invention relates to an aqueous concentrate which is stable with respect to freezing and defrosting and which contains at least one water-soluble or water-dispersible copper compound and, optionally, also a water-soluble or water-dispersible tin compound for use in a diluted state as a bath for the currentless copper plating or bronze plating of objects, especially metal objects such as iron or steel wires, characterized in that it contains at least one complexed water-soluble or water-dispersed copper compound. The invention also relates to an aqueous bath which contains at least one aqueous or water-dispersible copper compound and, optionally, a water-soluble or water-dispersible tin compound for the currentless copper plating of objects in addition to at least one brightening agent and which has an adjusted pH value of less than 2.5. The invention also relates to a method for currentless copper plating or bronze plating of an object, especially a metallic object.

Abstract: An integrated semiconductor memory includes word lines connected to a first voltage potential via a respective first controllable switch and a respective third controllable switch and to a second voltage potential via a respective second controllable switch. In order to test whether one of the word lines is connected to the first voltage potential via its respective first and third controllable switches, the one of the word lines is connected to a comparator circuit via the respective second controllable switch and a driver line. After the respective first and third controllable switches have been controlled into the on state, in a test operating state of the integrated semiconductor memory, the respective second controllable switch is controlled into the on state and a potential state on the word line is evaluated by the comparator circuit. The result of the evaluation is fed to an external data terminal by an evaluation signal.

Abstract: Integrated semiconductor circuits, in particular, dynamic random access memories include a multiplicity of generator circuits for generating internal voltage levels from an externally applied supply voltage. During testing, the internal voltage levels are altered by the output voltage generated at the output of the generator circuit being adapted to an externally applied test voltage. If the test voltage is outside a tolerance range, the semiconductor circuit maybe destroyed. A protection circuit connected in parallel with the generator circuit limits the output voltage.

Abstract: An integrated semiconductor memory, which can be operated in a normal operating state and a test operating state, includes a current pulse circuit with an input terminal for applying an input signal. The current pulse circuit is connected to an output terminal via an interconnect for carrying a current. In the test operating state, the current pulse circuit generates at least one first current pulse with a first, predetermined time duration in a first test cycle and at least one second current pulse with a second, unknown time duration in a subsequent second test cycle. In addition to a first current flowing on the interconnect in the normal operating state, a second current flows on the interconnect during the first test cycle and a third current flows during the second test cycle in the test operating state.

Abstract: An integrated circuit includes a circuit component, a first control circuit and a switchable resistance network. An input voltage is fed to the circuit component on the input side. A control signal generated by the first control circuit is fed to the control terminal of the circuit component. With the switchable resistance network, the first resistance or the second resistance is connected between an output terminal of the circuit component and the output terminal of the integrated circuit to generate a voltage drop between the input side and the output terminal of the circuit component. The integrated circuit makes it possible to generate a current at the output terminal of the circuit component in a manner dependent on the control signal and the voltage dropped between the input side and the output terminal of the circuit component. Families of characteristic curves of transistors of an integrated circuit are determined by the integrated circuit.

Abstract: An integrated circuit includes an input terminal (IN) for application of a supply voltage (Vext) and an output terminal (A) for generation of an output voltage (Vout). A first branch including a first controllable resistance (T1) and a second branch including a charge pump (10) and a second controllable resistance (T2) are connected between the input terminal (IN) and the output terminal (A). A control circuit (20) alters the resistance values of the first and second controllable resistances (T1, T2) in a manner dependent on a ratio of an actual value (Vout) of the output voltage to a desired value (VSout) of the output voltage and a ratio of an actual value (Vext) of the supply voltage to a desired value (VSext) of the supply voltage. As a result, the output voltage (Vout) can be stabilized to the desired value (VSout) virtually independently of fluctuations of the supply voltage.

Abstract: Method of effecting a readout of a gas-sensitive field-effect transistor having an air gap between a gate electrode with a gas-sensitive layer and the readout transistor, in which a potential occurring on the gas-sensitive layer in the presence of a target gas is passed through a noncontacting floating gate electrode to the transistor, wherein the potential of a reference electrode, which together with the floating gate electrode generates a capacitance Cw, is tracked to the potential of the floating gate electrode in order to eliminate the capacitance Cw during the measurement.