Abstract: A circuit configuration and a method for the synchronization of signals include transmitting signals in parallel through data lines and buffer-storing the signals in a synchronizing unit. A clock signal is determined from the signals of a data line and is used for synchronizing the outputting of the signals. The signals are output in the order in which the signals were read. The signals are likewise output through a plurality of data lines, the signals being output temporally synchronously. Propagation time differences are compensated due to the buffer-storage. Moreover, the clock signal is determined from the signals themselves. Consequently, the use of an additional clock signal is not necessary.

Abstract: Apparatus for signaling that a predetermined time value has elapsed.

Abstract: The invention relates to a semiconductor memory device having

Abstract: An electrical cooking appliance has at least one cooktop with cooking zones becoming hot in a switched-on state, an optical residual heat indicator indicating hot cooking zones when line voltage is applied to the cooking appliance, a counter system switching off the residual heat indicator with a time delay after the switching-off of the cooking appliance connected to line voltage occurs, and a line voltage detector for detecting a presence of the line voltage at the cooking appliance. Information is stored in a memory of the counter system as long as a counter reading is greater than zero, and, after a line voltage interruption, the residual heat indicator remains activated for a certain period of time, in dependence on the inquired memory content, if the information in the memory indicates a counter value greater than zero.

Abstract: A method for testing a memory circuit selects each cell in a region of a cell array as a target cell and performs a test cycle which includes selecting the target cell and neighboring cells which contain at least those cells for which is cannot be ruled out that their operation causes a fault-producing interaction. A data item is written to the target cell in order to produce one of two defined states. A write signal is applied to the neighboring cells in order to produce an undefined state which lies between the two defined states. The target cell and the neighboring cells are then read and the result of the reading process is used to check whether there is any interaction between the operation of the target cell and the operation of the neighboring cells.

Abstract: A method and a semiconductor component are described in which an internal voltage to be measured is divided via a matched voltage divider, and is passed to a selected connecting pin. Since there are normally no unused connecting pins, in, for example, present-day large scale integrated components, the connected module is disconnected from a selected connecting pin for a specific time period, and the divided measurement voltage is passed to the connecting pin. This is done by use of a controller, which operates appropriate switches. This method is preferably used for memory components such as DRAM, SRAM etc.

Abstract: An input circuit for an integrated memory is described. The input circuit for the integrated memory has a signal input line, a memory element, and a clock recovery unit with which a clock signal is generated from the input signal on the signal input line so that the input signal can be read into the memory element using the clock signal which is generated. A further input circuit is described which contains an oscillator. The oscillator generates a clock signal that can be synchronized with the input signal, it being possible to read the input signal into the memory element using the clock signal which is generated.

Abstract: A circuit configuration and a method for the synchronization of signals include transmitting signals in parallel through data lines and buffer-storing the signals in a synchronizing unit. A clock signal is determined from the signals of a data line and is used for synchronizing the outputting of the signals. The signals are output in the order in which the signals were read. The signals are likewise output through a plurality of data lines, the signals being output temporally synchronously. Propagation time differences are compensated due to the buffer-storage. Moreover, the clock signal is determined from the signals themselves. Consequently, the use of an additional clock signal is not necessary.

Abstract: The invention relates to a method for treating biogenic residues, especially cafeteria leftovers, meat refuse, clarification sludge, organic industrial wastes and the like, wherein the residues are subjected to temperature pressure hydrolysis. In order to obtain a higher flow rate for residues using a small apparatus, the invention provides that temperature pressure hydrolysis is carried out in a cylindrical section in a first direction and in an external radial section in a second direction, the second direction being opposite to the first direction.

Abstract: An integrated circuit includes a terminal supplying a digital signal, a controllable driver circuit connected to the terminal and outputting the digital signal, and a comparator device. An actuating circuit actuates the driver circuit as a function of a clock signal. The comparator device compares the timing of signal transitions of the clock signal with transitions of the digital signal. The comparator has a first comparator input for receiving the clock signal and a second comparator input connected to the driver output for receiving the digital signal. The comparator device outputs an output signal having a first state if a signal transition of the clock signal at the first input takes place before a signal transition of the digital signal at the second input, and outputs a second state if the clock signal transition takes place after digital signal transition. In a test mode, the invention compares the clock and digital signal timings with a high degree of accuracy.

Abstract: An electronic circuit in an integrated circuit having memory cells is described. The circuit permits information to be written to particular memory cells only once, so that subsequent writing to the particular memory cells is blocked. The circuit is used in a test structure for integrated circuits on a wafer. A method for testing integrated circuits on a wafer that are connected to a test apparatus is also described. Once the supply voltage to a first circuit to be tested has been turned on, a preliminary test is carried out to ascertain parameters that need to be set. The supply voltage is then applied to a next circuit to be tested, a preliminary test is carried out, and memory cells have information written to them, until the parameters have been set for all the connected circuits to be tested. The test apparatus then carries out the actual operational test in parallel for all the connected circuits to be tested.

Abstract: For testing, a reference clock signal is applied to a first delay path having a fixed delay and a second delay path having a variable delay. The delay paths are connected to inputs of a clocked circuit to initiate data transfer and they apply a clock signal and a data signal, respectively. The variable delay is set within the range [tF−n&Dgr;t/2; tF+n&Dgr;t/2]. The fixed delay tF is at least n&Dgr;t/2. For calibration, the setting range of the variable delay and the fixed delay are each increased to the k-fold value and the variable delay is incremented in steps from n=0 until three phase changes are detected. The value of n at the first phase cycle completion corresponds to the variable delay for the set-up time and the value of n at the third phase cycle completion corresponds to the variable delay for the hold time.

Abstract: An integrated circuit includes a terminal supplying a digital signal, a controllable driver circuit connected to the terminal and outputting the digital signal, and a comparator device. An actuating circuit actuates the driver circuit as a function of a clock signal. The comparator device compares the timing of signal transitions of the clock signal with transitions of the digital signal. The comparator has a first comparator input for receiving the clock signal and a second comparator input connected to the driver output for receiving the digital signal. The comparator device outputs an output signal having a first state if a signal transition of the clock signal at the first input takes place before a signal transition of the digital signal at the second input, and outputs a second state if the clock signal transition takes place after digital signal transition. In a test mode, the invention compares the clock and digital signal timings with a high degree of accuracy.

Abstract: A circuit configuration for reducing disturbances due to a switching of an output driver. The output driver has a plurality of output driver stages and a delay element. The delay element increases the signal delay of the switch-on or switch-off signals for the output driver stages with an increasing supply voltage.

Abstract: A pulse shaper circuit includes a buffer having an input, an output and two supply connections. A controllable first switch is connected between one of the supply connections and a first supply potential, a controllable second switch is connected between the other supply voltage connection and a second supply potential, a controllable third switch is connected between the output of the buffer and the first supply potential and a controllable fourth switch is connected between the output of the buffer and the second supply potential. A control device for the switches is connected to the output of the buffer and produces a first control pulse of a specific duration at the occurrence of first edges of a signal present at the output of the buffer and a second control pulse of a specific duration at the occurrence of second edges. The first control pulse changes over the first switch from the ON state to the OFF state and the fourth switch from the OFF state to the ON state.

Abstract: An RS flip-flop has an inverter, connected to an input terminal of the RS flip-flop, a NOR gate having an Enable-Set input, a NAND gate having an Enable-Reset input, and a first and a second transistor connected to the inverter. The outputs of the NOR and NAND gates are connected, via the gate paths of the first and second transistors, to the gate electrode of a third and a fourth transistor, respectively. The third and the fourth transistor are connected in series and form a holding element, whose common connection point is connected to the output of the inverter and to the output terminal of the flip-flop.

Abstract: A rotating closure device for a runout opening in a base of a metallurgical vessel for preventing access of gases reacting with a melt. The device includes an upper closure plate (3) positioned at an end side of a drain block (1) and a lower closure plate (4) at the outlet (2). The upper closure plate (3) is provided with at least two through-holes for meeting at least two channels (7, 8) in the drain block (1), which channels (7, 8) extend parallel to an axis of rotation of the device. The lower closure plate (4) is provided with at least one through-hole for meeting at least one channel (6) in the outlet. The at least two chapels (7, 8) meet at least one channel (6) via a connection between the upper and lower closure plates (3, 4).

Abstract: The invention is directed to a process and apparatus for preheating and transferring scrap into smelting furnaces for steelmaking or the like. The scrap is preheated by energy contained in the waste gases from the smelting furnace, which energy comprises sensible heat and chemically bonded heat in the combustible portions of the waste gases. The furnace-waste gases are guided to a waste-gas combustion chamber incorporated in a waste-gas outlet line and are burned therein with air to generate hot combustion gases which are fed to the scrap in the receptacles at a preheating station and then sucked out via an exhaust fan. After the scrap reaches the desired temperature, the receptacle containing the preheated scrap is removed from the preheating station so that the preheated scrap may be transferred to the smelting furnace. During this receptacle changeover process, the hot combustion gases are rerouted to another scrap-filled receptacle at the preheating station using a pipeline arrangement.

Abstract: The mold continuous casting of metals includes a stationary base frame; a support plate within the base frame, the support plate including first and second opposed sides; a metallic shaping wall mounted on the support plate and having a longitudinal axis in the direction of casting; a carrier plate attached to the base frame; a plurality of spring elements each having two ends and being uniformly distributed over and fastened at one end thereof to the first side of the support plate, the other ends of the spring elements being fastened to the carrier plate, the first side of the support plate facing away from the shaping wall, the spring elements extending in a direction transverse to the direction of casting and having a stiffness which is substantially less in the direction of casting than in the two directions transverse thereto.

Abstract: The invention concerns an electro-metal smelting furnace with at least one taphole located at the bottom with which hole is associated a closure equipped with a drive.