Abstract: An integrated semiconductor memory, and method for operating such a memory, in particular a DRAM memory, having local data lines (LDQT, LDQC) segmented in the column direction (Y), which local data lines can be connected by a CSL switch in response to a column select signal fed via a CSL line (CSL) running in the row direction (X) to primary sense amplifiers for transferring or accepting spread data signals to or from bit lines of the respective segment (I, II, III), LDQ switches are arranged at the interfaces between adjacent segments of the local data lines (LDQT, LDQC) for their connection to the local data lines (LDQT, LDQC) of adjacent segments (I, II, III). LDQ switches, depending on a control signal fed separately to each of said LDQ switches, are closed during a precharge phase, which takes place before each read cycle, of at least two adjacent LDQ segments.

Abstract: A voltage generator arrangement supplies a largely constant output voltage with a high current driver capability. A bandgap reference circuit is downstream from an impedance converter and downstream a voltage generator. The bandgap reference circuit and the impedance converter on the one hand and the voltage generator on the other hand are connected to different reference ground potential line. The impedance converter contains a charge pump circuit to provide increased control potential, which drives the voltage generator. The voltage generator in contrast produces a reduced output potential. The influence of any voltage drop on that reference ground potential line to which the voltage generator is connected in the output potential is thus likewise reduced.

Abstract: A method for testing a memory circuit selects each cell in a region of a cell array as a target cell and performs a test cycle which includes selecting the target cell and neighboring cells which contain at least those cells for which is cannot be ruled out that their operation causes a fault-producing interaction. A data item is written to the target cell in order to produce one of two defined states. A write signal is applied to the neighboring cells in order to produce an undefined state which lies between the two defined states. The target cell and the neighboring cells are then read and the result of the reading process is used to check whether there is any interaction between the operation of the target cell and the operation of the neighboring cells.

Abstract: A memory chip having an integrated address scrambler unit that has address inputs for applying an address and can be to scramble the address in various ways depending on control bits. In addition, a memory cell array is provided, which is connected downstream of the address scrambler unit. This allows an increase in flexibility during scrambling.

Abstract: The invention relates to a process for generating a synchronizer pulse, in particular a clock pulse, as well as a synchronizer signal generator device, which is connected to an electronic system, and which emits a synchronizer signal of a particular frequency, which is transferred to at least one device of the electronic system, whereby at least one device is provided with its impedance selected so that a resonance oscillatory circuit—of which the resonance essentially coincides with the frequency of the synchronizer signal—is created for the synchronizer signal generator device.

Abstract: A method includes providing a semiconductor memory device having at least one memory cell array. The memory cell array has a multiplicity of memory cells arranged in a matrix-like manner. Each of the memory cells is assigned a physical address and an electrical address. The method also includes inputting a physical address of a memory cell that is to be addressed into an address input device of the semiconductor memory device, decoding the input physical address into the assigned electrical address of the memory cell to be addressed by an address decoder device of the semiconductor memory device, and outputting the electrical address to the memory cell array in order to address the memory cell.

Abstract: The invention relates to a RAM store having a shared SA structure, in which sense amplifiers (SA) arranged in SA strips (10) between two respective adjacent cell blocks are used by a plurality of bit line pairs (21, 22; 21-24) from the adjacent cell blocks and the bit line pairs (21, 22; 21-24) have respective charge equalization circuits individually associated with them for the purpose of performing charge equalization between the bit line halves of the bit line pairs (21, 22; 21-24) in a precharge phase, where a shorting transistor (30) is provided which, when prompted by a control signal (EQLx), connects the bit line halves (BLT, BLC) of the bit line pairs (21, 22; 21-24) which are in the precharge phase to one another.

Abstract: In a driver circuit having a plurality of drivers for driving signals in parallel, the drivers are each connected to an input signal line for receiving a respective input signal and to an output signal line for outputting a respective driven output signal. An output signal line of one of the drivers may be connected, via a switch or switching means, to an output signal line of another of the drivers. A control circuit is connected to one of the drivers and is used to drive the switch or switching means in such a manner that the switching means can be activated, for charge equalization, by the control circuit following a driving operation in one of the drivers. A respective associated memory circuit, by which an associated logic circuit for driving one of the switch or switching means is connected to the relevant output signal line, is connected to the respective output signal line. Overall power consumption of the driver circuit can be minimized.

Abstract: An integrated memory contains a memory cell array, which has word lines and bit lines, and a read/write amplifier, which is connected to the bit lines for the assessing and amplifying data signals. A voltage generator circuit generates a voltage supply for application to the read/write amplifier. A potential difference is applied to the read/write amplifier using different supply potentials. The voltage generator circuit increases the potential difference applied to the read/write amplifier for a limited period of time during an assessment and amplification operation of the read/write amplifier. Charge-dependent control is implemented in the voltage generator circuit. An assessment and amplification operation can be carried out at a comparatively high switching speed and a low power consumption is possible.

Abstract: An integrated dynamic memory includes memory cells which are combined to form individual independently addressable units, and a control circuit for controlling a refresh mode for the memory cells. The memory cells can have their memory cell content refreshed. The control circuit is designed such that one or more units of memory cells can be subject to a refresh mode in parallel in a refresh cycle. The control circuit sets a number of memory cell units, which are to be refreshed in parallel in a refresh cycle based on a temperature reference value. A maximum possible operating temperature for a memory chip can be increased without additional restrictions on memory access.

Abstract: An electrical cooking appliance has at least one cooktop with cooking zones becoming hot in a switched-on state, an optical residual heat indicator indicating hot cooking zones when line voltage is applied to the cooking appliance, a counter system switching off the residual heat indicator with a time delay after the switching-off of the cooking appliance connected to line voltage occurs, and a line voltage detector for detecting a presence of the line voltage at the cooking appliance. Information is stored in a memory of the counter system as long as a counter reading is greater than zero, and, after a line voltage interruption, the residual heat indicator remains activated for a certain period of time, in dependence on the inquired memory content, if the information in the memory indicates a counter value greater than zero.

Abstract: The invention relates to an integrated semiconductor memory, in particular a DRAM memory, in which primary sense amplifiers (SA) are coupled to a bit line (BL) of a respective cell block and can be connected to a common local data line (LDQ) by means of a respective assigned CSL switch in response to a CSL signal and in which an MDQ/LDQ switch arrangement connects a main data line (MDQ) to the local data line (LDQ) of a respective cell block in response to an MDQ/LDQ switch signal. In the case of the semiconductor memory, a control input of each CSL switch is connected to an AND element, which ANDs the CSL signal with the MDQ/LDQ switch signal and thereby activates the CSL switches only in cell blocks in which a word line has been activated.

Abstract: An integrated semiconductor memory, and method for operating such a memory, in particular a DRAM memory, having local data lines (LDQT, LDQC) segmented in the column direction (Y), which local data lines can be connected by a CSL switch in response to a column select signal fed via a CSL line (CSL) running in the row direction (X) to primary sense amplifiers for transferring or accepting spread data signals to or from bit lines of the respective segment (I, II, III), LDQ switches are arranged at the interfaces between adjacent segments of the local data lines (LDQT, LDQC) for their connection to the local data lines (LDQT, LDQC) of adjacent segments (I, II, III). LDQ switches, depending on a control signal fed separately to each of said LDQ switches, are closed during a precharge phase, which takes place before each read cycle, of at least two adjacent LDQ segments.

Abstract: A voltage generator arrangement supplies a largely constant output voltage with a high current driver capability. A bandgap reference circuit drives a voltage generator on the output side, if necessary via an impedance converter. The bandgap reference circuit and the impedance converter on the one hand, and the voltage generator on the other hand, are connected to different reference ground potential lines. The voltage generator on the output side is preceded by a correction circuit, which corrects for the voltage drop on that reference ground potential line to which the output-side voltage generator is connected. The voltage generator arrangement is suitable for a greater integration density.

Abstract: A voltage generator arrangement supplies a largely constant output voltage with a high current driver capability. A bandgap reference circuit is downstream from an impedance converter and downstream a voltage generator. The bandgap reference circuit and the impedance converter on the one hand and the voltage generator on the other hand are connected to different reference ground potential line. The impedance converter contains a charge pump circuit to provide increased control potential, which drives the voltage generator. The voltage generator in contrast produces a reduced output potential. The influence of any voltage drop on that reference ground potential line to which the voltage generator is connected in the output potential is thus likewise reduced.

Abstract: For testing, a reference clock signal is applied to a first delay path having a fixed delay and a second delay path having a variable delay. The delay paths are connected to inputs of a clocked circuit to initiate data transfer and they apply a clock signal and a data signal, respectively. The variable delay is set within the range [tF−n&Dgr;t/2; tF+n&Dgr;t/2]. The fixed delay tF is at least n&Dgr;t/2. For calibration, the setting range of the variable delay and the fixed delay are each increased to the k-fold value and the variable delay is incremented in steps from n=0 until three phase changes are detected. The value of n at the first phase cycle completion corresponds to the variable delay for the set-up time and the value of n at the third phase cycle completion corresponds to the variable delay for the hold time.

Abstract: An integrated test circuit, as part of an integrated circuit, includes phase-shifted test signals fed through inputs A and B. These test signals are conducted through a plurality of cascaded delay elements, the advancing of the first test signal through the delay elements being held and evaluated by the second test signal.

Abstract: A method and a semiconductor component are described in which an internal voltage to be measured is divided via a matched voltage divider, and is passed to a selected connecting pin. Since there are normally no unused connecting pins, in, for example, present-day large scale integrated components, the connected module is disconnected from a selected connecting pin for a specific time period, and the divided measurement voltage is passed to the connecting pin. This is done by use of a controller, which operates appropriate switches. This method is preferably used for memory components such as DRAM, SRAM etc.

Abstract: An electronic circuit in an integrated circuit having memory cells is described. The circuit permits information to be written to particular memory cells only once, so that subsequent writing to the particular memory cells is blocked. The circuit is used in a test structure for integrated circuits on a wafer. A method for testing integrated circuits on a wafer that are connected to a test apparatus is also described. Once the supply voltage to a first circuit to be tested has been turned on, a preliminary test is carried out to ascertain parameters that need to be set. The supply voltage is then applied to a next circuit to be tested, a preliminary test is carried out, and memory cells have information written to them, until the parameters have been set for all the connected circuits to be tested. The test apparatus then carries out the actual operational test in parallel for all the connected circuits to be tested.

Abstract: An integrated test circuit, as part of an integrated circuit, includes phase-shifted test signals fed through inputs A and B. These test signals are conducted through a plurality of cascaded delay elements, the advancing of the first test signal through the delay elements being held and evaluated by the second test signal.