Abstract: A memory having a memory array having a plurality of word lines, a plurality of bit cells coupled to the word lines, and a plurality of control memory cells coupled to the word lines. Each word line of the plurality of word lines has a control memory cell coupled thereto and each control memory cell has an output. The memory also has a plurality of logic circuits coupled to the plurality of word lines. The output of each control memory cell is coupled to a corresponding one of the plurality of logic circuits. The plurality of logic circuits prevents access to the word line selected by a row address if the output of the control memory cell coupled to the selected word line is in a first logic state.

Abstract: A memory cell includes a first bi-directional resistive element having a cathode coupled to a first power rail and an anode coupled to an internal node, a second bi-directional resistive element having a cathode coupled to the internal node and an anode coupled to a second power rail, and a first transistor having a control electrode coupled to the internal node, a first current electrode coupled to a first bitline, and a second current electrode coupled to a third power rail.

Abstract: Temperature sensing circuitry implemented on a semiconductor integrated circuit that senses the temperature at a site, digitizes the sensed temperature, and then outputs a signal representing such a sensed temperature. The temperature sensing circuitry converts a voltage signal that is proportional to the temperature to a frequency-based signal, which is converted to a digital bit value. A scalar factor is applied to another voltage signal that is inversely proportional to the temperature to produce a scaled voltage signal. The scaled voltage signal is converted to a second frequency-based signal, which is converted to a digital bit value, and then the two digital bit values are compared. The temperature is determined when the digital bit values substantially match.

Abstract: Structures for substituting single bits in an array may include a first array having a plurality of word lines, and for each of the plurality of word lines a memory operable to store a bit substitution column value, and a first data output line operable to communicate the bit substitution column value to a write data shifter. The bit substitution column value may be associated with a bit substitution column in a second array, and the write data shifter may be operable to substitute the bit by shifting data to a redundancy column in the first array.

Abstract: A content addressable memory (CAM) includes a first entry which includes one or more bits, a second entry which includes one or more bits, first comparison circuitry configured to compare each bit of a comparand to a corresponding bit of the one or more bits of the first entry and to provide a hit/miss indicator in response thereto, and second comparison circuitry configured to compare each bit of the one or more bits of the first entry to a corresponding bit of the one or more bits of the second entry and to provide a fault indicator in response thereto.

Abstract: A method for minimizing soft error rates within caches by configuring a cache with a certain way which is more resistant to soft errors and then using this way to store modified data. In certain embodiments, the memory is made more soft error resistant by increasing a voltage across bitcells of the cache.

Abstract: A method for minimizing soft error rates within caches by configuring a cache with certain sections to correspond to bitcell topologies that are more resistant to soft errors and then using these sections to store modified data.

Abstract: A device (300, 1000) provides a dual-edge triggered flip-flop (DETFF) that is reconfigurable to a master-slave flip-flop (MSFF). The device includes a reconfigurable MUX-D flip-flop including two distinct circuit configurations. In a first configuration, two latches or storage elements (340, 360, 1040, 1060) are operating in series to provide a MUX-D flip-flop. In a second configuration, the storage elements (340, 360, 1040, 1060) are operating in parallel to provide a dual-edge triggered flip-flop (DETFF).

Abstract: A method and apparatus are provided for error correction of a memory by using a first memory (18), second memory (14), and redundant memory (19) to perform error correction code (ECC) processing on data retrieved from the first memory (18) by using the redundant memory (19) to replace entries in the second memory (14) having repeat addresses, thereby freeing entries in the second memory (14) for use in detecting and managing errors identified by the ECC processing.

Abstract: A circuit for determining a threshold indication of temperature with respect to a threshold temperature. The circuit includes a timer circuit and a temperature sensor circuit having an counter whose output has a relationship to temperature. At the end of a period determined by the timer circuit, a comparator circuit compares the count of the counter with an indication of the threshold temperature to determine a state of the threshold indication. In response to a change in state of the threshold indication, the circuit changes one of the count time or the counter output's relationship to temperature to provide a hysteresis for the threshold indication.

Abstract: A pipeline circuit determines a first effective address based a sum of a first value and a second value. The first effective address is based upon an actual value of a carry-in into a bit-wise region of the first and second values. The bit-wise region includes a predefined internal region of bits of the first and second values. The pipeline circuit also determines a second effective address based a sum of a third value and a fourth value. A collision detector circuit receives bits from the bit-wise region of each of the four values and determines a plurality of speculative results based upon the bits of the bit-wise regions and based upon a plurality of speculative carry-in values. A collision indicator is asserted based on at least one result of the plurality of speculative results, and the actual values of the first and second carry-in.

Abstract: Circuit embodiments of a multistage voltage regulator circuit are presented, where a circuit includes a first stage that includes a first bias transistor having a current terminal coupled to a first regulated node. The circuit also includes a second stage that includes a second bias transistor having a current terminal coupled to a second regulated node. The circuit also includes a third stage including a third bias transistor having a current terminal coupled to a third node. The circuit also includes a control loop for regulating voltages at the first and second regulated nodes, where the second regulated node is connected to a control terminal of the first bias transistor; and where the first regulated node is connected to a control terminal of the third bias transistor.

Abstract: A memory device includes a plurality of sense amplifiers, an array of memory cells including a first subset of memory cells, and a plurality of word lines. Each word line is coupled to each memory cell in a respective row of the memory cells and each row of the memory cells includes one memory cell of the first subset of memory cells. Each of a plurality of control word lines is coupled to a respective one of the memory cells in the first subset of memory cells and each of the memory cells in the first subset of memory cells generates a sense amplifier control signal coupled to control operation of a respective one of the plurality of sense amplifiers.

Abstract: A buffer circuit comprising a capacitor, the capacitor comprising a first terminal and a second terminal, an input signal being coupled to the first terminal; a first buffer stage coupled to the second terminal of the capacitor such that the input signal is capacitively coupled to the first buffer stage; and, a pulse generator coupled to control the first buffer stage, the pulse generator being configured to generate a control pulse corresponding to a hold time of the first buffer stage such that the buffer circuit detects a transition of the input signal during the hold time.

Abstract: A method for controlling a memory scrubbing rate based on content of the status bit of a tag array of a cache memory. More specifically, the tag array of a cache memory is scrubbed at smaller interval than the scrubbing rate of the storage arrays of the cache. This increased scrubbing rate is in appreciation for the importance of maintaining integrity of tag data. Based on the content of the status bit of the tag array which indicates modified, the corresponding data entry in the cache storage array is scrubbed accordingly. If the modified bit is set, then the entry in the storage array is scrubbed after processing the tag entry. If the modified bit is not set, then the storage array is scrubbed at a predetermined scrubbing interval.

Abstract: A method for minimizing soft error rates within caches by controlling a memory scrubbing rate selectively for a cache memory at an individual bank level. More specifically, the disclosure relates to maintaining a predetermined sequence and process of storing all modified information of a cache in a subset of ways of the cache, based upon for example, a state of a modified indication within status information of a cache line. A cache controller includes a memory scrubbing controller which is programmed to scrub the subset of the ways with the modified information at a smaller interval (i.e., more frequently) compared to the rest of the ways with clean information (i.e., information where the information stored within the main memory is coherent with the information stored within the cache).

Abstract: A method of operating a circuit includes receiving a first data signal at a first node. The first node is coupled to a second node to couple the first data signal to the second node. After coupling the first node to the second node, an inversion is enabled from the second node to a third node. An inversion from the third node to the fourth node is provided. After the enabling the inversion from the second node to the third node, the first node is decoupled from the second node. After the enabling the inversion from the second node to the third node, the second node is coupled to the third node. An inversion from the fourth node to the third node is enabled and the second node is decoupled from the fourth node.

Abstract: A voltage regulator includes a regulating transistor and a control circuit. The regulating transistor has a first current electrode for providing a regulated voltage, a second current electrode, and a control electrode. The control circuit has an output coupled to the control electrode of the regulating transistor, and an input coupled to the first current electrode of the regulating transistor. The control circuit includes a first inverting gain stage having a first load element, and a second inverting gain stage having a second load element. One of the first or second load elements is characterized as being a diode and the other of the first or second load elements is biased by a bias circuit.

Abstract: A method and data processing system for accessing an entry in a memory array by placing a tag memory unit (114) in parallel with an operand adder circuit (112) to enable tag lookup and generation of speculative way hit/miss information (126) directly from the operands (111, 113) without using the output sum of the operand adder. PGZ-encoded address bits (0:51) from the operands (111, 113) are applied with a carry-out value (Cout48) to a content-addressable memory array (114) to generate two speculative hit/miss signals. A sum value (EA51) computed from the least significant base and offset address bits determines which of the speculative hit/miss signals is selected for output (126).

Abstract: A configurable flip-flop can be operated in a normal mode and a buffer mode. In the normal mode, the flip-flop latches data at the flip-flop input based on a clock signal. In the buffer mode, the flip-flop provides data at the flip-flop input to the flip-flop output, independent of the clock signal.