Abstract: In a digital control power supply, a mode control unit measures a first frequency and a second frequency for a difference between a second digital value and a target value. Based on the measured first frequency and second frequency and a predetermined threshold set to the first and second frequencies, the mode control unit determines whether an amplification factor for use in amplification processing by an amplifier is maintained at a current amplification factor or is changed to an amplification factor which is larger or smaller by 1 than the current amplification factor. This contributes to an improvement in noise resistance of the digital control power supply and prevents an output voltage from being unstable.

Abstract: A semiconductor device for use in a power supply circuit has first and second MOSFETS. The source-drain path of one of the MOSFETS are coupled to the source-drain path of the other, and a load element is coupled to a connection node of the source-drain paths. The second MOSFET is formed on a semiconductor substrate with a Schottky barrier diode. First gate electrodes of the second MOSFET are formed in trenches in a first region of the semiconductor substrate, while second gate electrodes of the second MOSFET are formed in trenches in a second region of the semiconductor substrate. The first and second gate electrodes are electrically connected together. Portions of the Schottky barrier diode are formed between adjacent ones of the second gate electrodes. A center-to-center spacing between adjacent first gate electrodes is smaller than a center-to-center spacing between adjacent second gate electrodes.

Abstract: Provided is a semiconductor device which allows an alignment mark used for the manufacturing of a solid-state image sensor (semiconductor device) having a back-side-illumination structure to be formed in a smaller number of steps. The semiconductor device includes a semiconductor layer having a first main surface and a second main surface opposing the first main surface, a plurality of photodiodes which are formed in the semiconductor layer and in each of which photoelectric conversion is performed, a light receiving lens disposed over the second main surface of the semiconductor layer to supply light to each of the photodiodes, and a mark for alignment formed inside the semiconductor layer. The mark for alignment is formed so as to extend from the first main surface toward the second main surface and have a protruding portion protruding from the second main surface in a direction toward where the light receiving lens is disposed.

Abstract: The disclosed invention provides a semiconductor device capable of suitably controlling the level of an enable signal to resolve NBTI in a PMOS transistor. An input node receives an input signal alternating between high and low levels during normal operation and fixed to a high level during standby. A detection unit receives a signal through the input node and outputs an enable signal. The detection unit sets the enable signal to a low level upon detecting that the input node remains at a high level for a predetermined period. A signal transmission unit includes a P-channel MOS transistor and transmits a signal input to the input node according to control by the enable signal.

Abstract: A semiconductor device is provided, in which it becomes easy to reliably couple a plug conductive layer and a wiring layer located over the plug conductive layer to each other and falling of the wiring can be suppressed. The plug conductive layer contacts a source/drain region formed over a major surface of the semiconductor substrate. A contact conductive layer is formed so as to contact both the upper surface and the side surface of the plug conductive layer. Wiring layers are formed over the contact conductive layer so as to be electrically coupled to the contact conductive layer.

Abstract: To actualize a reduction in the on-resistance of a small surface mounted package having a power MOSFET sealed therein. A silicon chip is mounted on a die pad portion integrated with leads configuring a drain lead. The silicon chip has, on the main surface thereof, a source pad and a gate pad. The backside of the silicon chip configures a drain of a power MOSFET and bonded to the upper surface of a die pad portion via an Ag paste. A lead configuring a source lead is electrically coupled to the source pad via an Al ribbon, while a lead configuring a gate lead is electrically coupled to the gate pad via an Au wire.

Abstract: Disclosed is a miniaturized semiconductor device having an SOI layer, in which: a silicon layer is formed over a semiconductor substrate via an BOX film; after the silicon layer is patterned by using a nitride film as a mask, an insulating film covering the surface of each of the nitride film, the silicon layer, and the BOX film is formed; subsequently, an opening, which penetrates the insulating film and the BOX film and which exposes the upper surface of the semiconductor substrate, is formed, and an epitaxial layer is formed in the opening; subsequently, the SOI region and a bulk silicon layer are formed over the semiconductor substrate by flattening the upper surface of the epitaxial layer with the use of the nitride film as an etching stopper film.

Abstract: To improve a manufacture yield of semiconductor devices each including an IGBT, an active region defined by an insulating film and where an element of an IGBT is formed has a first long side and a second long side spaced at a predetermined distance apart from each other and extended in a first direction in a planar view. One end of the first long side has a first short side forming a first angle with the first long side, and one end of the second long side has a second short side forming a second angle with the second long side. The other end of the first long side has a third short side forming a third angle with the first long side, and the other end of the second long side has a fourth short side forming a fourth angle with the second long side. The first angle, the second angle, the third angle, and the fourth angle are in a range larger than 90 degrees and smaller than 180 degrees.

Abstract: A semiconductor device in which misalignment does not cause short-circuiting and inter-wiring capacitance is decreased. Plural wirings are provided in a first interlayer insulating layer. An air gap is made between at least one pair of wirings in the layer. A second interlayer insulating layer lies over the wirings and first interlayer insulating layer. The first bottom face of the second interlayer insulating layer is exposed to the air gap. When a pair of adjacent wirings whose distance is shortest are first wirings, the upper ends of the first interlayer insulating layer between the first wirings are in contact with the first wirings' side faces. The first bottom face is below the first wirings' upper faces. b/a?0.5 holds where a represents the distance between the first wirings and b represents the width of the portion of the first interlayer insulating layer in contact with the first bottom face.

Abstract: Over a semiconductor substrate, a gate insulating film including an interfacial layer, a HfON film, and a HfSiON film is formed. Then, over the HfSiON film, an Al-containing film and a mask layer are formed. Subsequently, the mask layer and the Al-containing film are selectively removed from an n-channel MISFET formation region. Then, a rare-earth-element-containing film is formed over the HfSiON film in the n-channel MISFET formation region and over the mask layer in a p-channel MISFET formation region. Heat treatment is performed to cause a reaction between each of the HfON film and the HfSiON film and the rare-earth-element-containing film in the n-channel MISFET formation region and cause a reaction between each of the HfON film and the HfSiON film and the Al-containing film in the p-channel MISFET formation region. Thereafter, the unreacted rare-earth-element-containing film and the mask layer are removed, and then metal gate electrodes are formed.

Abstract: A conventional semiconductor device used for a power supply circuit such as a DC/DC converter has problems of heat dissipation and downsizing, in particular has the problems of heat dissipation and others in the event of downsizing. A semiconductor device has a structure formed by covering a principal surface of a semiconductor chip having the principal surface and a plurality of MIS type FETs formed over the principal surface with a plurality of metal plate wires having pectinate shapes; allocating the pectinate parts alternately in a planar view over the principal surface; and further electrically coupling the plural metal plate wires to a plurality of terminals.

Abstract: To suppress stress variation on a channel forming region, a semiconductor device includes an element isolating region on the semiconductor substrate principal surface, and an element forming region on the principal surface to be surrounded by the element isolating region. The principal surface has orthogonal first and second directions. A circumferential shape of the element forming region has a first side extending along the first direction. The element forming region has a first transistor region (TR1), a second transistor region (TR2) arranged between the first side and TR1, and a dummy region on the first direction side of TR1. TR1 has a first channel forming region facing the first side. TR2 has a second channel forming region facing the first side. The first channel forming region has a non-facing region that is not facing the second channel forming region. The dummy region faces the non-facing region in the second direction.

Abstract: A semiconductor device for realizing higher-precision noise elimination includes: a decoder which decodes an encoded input signal; a determining unit which determines whether or not a voice signal is included in the input signal; a suppressor which performs a suppressing process for suppressing a noise component included in the input signal on the basis of a result of determination by the determining unit; and a first storage for storing, as a determination criterion value used for the determination, a first criterion value which specifies the proportion of a voice signal with respect to voice distortion noise.

Abstract: Low-k porous insulating films with a high modulus of elasticity are made by depositing alkylated cyclic siloxane precursors over a semiconductor substrate by CVD. Plasma enhancement of the CVD is performed either during CVD or in situ on the deposited film. A UV cure of the film is effected under controlled temperature and time conditions, which generates a tight bonding structure between adjacent ring moieties without disrupting the Si—O ring bonding.

Abstract: The present invention provides a liquid crystal display controller device and method which provides for a full and/or partial display with good display quality and/or low power consumption based on the scanning period for an active scan line being dependent upon a number of reference clock pulses. Some embodiments of the present invention include one or more of the following features: keeping the frequency substantially constant for different numbers of active scan lines, allowing change of the frequency due to characteristics of the LCD, displaying gradation with near linear effective voltage characteristics, displaying graduation data with lower power, or displaying a partial or full screen in a mobile device, for example, a cell phone.

Abstract: The present invention prevents bumps on semiconductor chips from sticking to probe needles and coming off from the semiconductor chips. A wafer has effective areas where a plurality of bumps (first bumps) are formed. The bumps are formed on the side of an active surface of the semiconductor chips. The wafer further has non-effective areas where a plurality of dummy bumps are formed. Among the dummy bumps, some positioned at the outermost circumference are dummy bumps (second bumps) that are smaller than the other bumps. The dummy bumps (second bumps) intersect the inner peripheral edge of a shielding member as viewed in a plan view. The dummy bumps (second bumps) are formed over third pad electrodes. A bump-formation insulating film is removed from over the entire third pad electrodes.

Abstract: A restriction is given to the calculation function for image processing achieved by the hard-wired system and the memory access control of a buffer memory, and a range of the restriction is made variable by a program control and others. Data is inputted to the buffer memory from the outside with a restriction of “in units of memory line”, and the number of memory lines and positions of the same to which data is inputted can be programmable by the control circuit. The arithmetic circuit is subjected to the restriction of performing the calculation in units of data of one or plural memory lines supplied from the buffer memory, and a calculation processing content in units of calculation processing for the units of data can be programmably assigned by the control circuit.

Abstract: The performances of semiconductor elements disposed in a multilayer wiring layer are improved. A semiconductor device includes: a first wire disposed in a first wiring layer; a second wire disposed in a second wiring layer stacked over the first wiring layer; a gate electrode arranged between the first wire and the second wire in the direction of stacking of the first wiring layer and the second wiring layer, and not coupled with the first wire and the second wire; a gate insulation film disposed over the side surface of the gate electrode; and a semiconductor layer disposed over the side surface of the gate electrode via the gate insulation film, and coupled with the first wire and the second wire.

Abstract: Disclosed is a semiconductor device including a semiconductor chip and a semiconductor package. The semiconductor package includes an antenna formed of a lead frame, a first wire that connects the antenna and a first electrode pad of the semiconductor chip, and a second wire that connects the antenna and a second electrode pad of the semiconductor chip. The semiconductor chip is disposed in one of four regions in the semiconductor package sectioned by line segments connecting midpoints of two pairs of opposing sides of the semiconductor package. A centroid of the semiconductor chip is positioned outside a closed curve composed of a straight line segment connecting a first connection point where the antenna and the first wire are connected and a second connection point where the antenna and the second wire are connected, and a line connecting the first and second connection points along the antenna.

Abstract: The present invention provides a non-insulated type DC-DC converter having a circuit in which a power MOS•FET for a high side switch and a power MOS•FET for a low side switch are connected in series. In the non-insulated type DC-DC converter, the power transistor for the high side switch, the power transistor for the low side switch, and driver circuits that drive these are respectively constituted by different semiconductor chips. The three semiconductor chips are accommodated in one package, and the semiconductor chip including the power transistor for the high side switch, and the semiconductor chip including the driver circuits are disposed so as to approach each other.