Abstract: A password authentication circuit includes a timer that measures first and second periods of a password authentication period, a control circuit that, in a first period, disables writing of a password received into a password register, in a predetermined period within a second period enables writing of a password received into the password register and outside the predetermined period within the second period disables writing of a password received into the password register; a password comparison unit that compares a password in the password register and a password expected value to perform authentication of the password; and a first period generation unit that controls variably the first period, a password last written into the password register in the predetermined period of the second period being made a target for authentication.

Abstract: First, a porous insulating film 120 is formed using an organic silica raw material containing a hydrocarbon group. The hydrocarbon group contains, for example, an unsaturated carbon compound, but may contain a saturated carbon compound. The skeleton of the organic silica is, for example, cyclic organic silica. Next, the surface of the porous insulating film 120 is subjected to plasma processing by using a processing gas containing an inactive gas and a reducing gas. Subsequently, in the porous insulating film 120, a wiring trench 123 is formed and is embedded with wiring 124.

Abstract: A semiconductor device includes a first insulating layer (interlayer insulating layer), a resistive element that is disposed over the first insulating layer (interlayer insulating layer) and at least a surface layer of which is a TaSiN layer, and an interlayer insulating layer disposed over the first insulating layer (interlayer insulating layer) and the resistive element. Multiple via plugs having ends coupled to the TaSiN layer are disposed in the interlayer insulating layer.

Abstract: A first nitride semiconductor layer contains Ga. The first nitride semiconductor layer is, for example, a GaN layer, an AlGaN layer, or an AlInGaN layer. Then, an aluminum oxide layer has tetra-coordinated Al atoms each surrounded by four O atoms and hexa-coordinated Al atoms each surrounded by six O atoms as Al atoms in the interface region with respect to the first nitride semiconductor layer. The interface region is a region apart, for example, by 1.5 nm or less from the interface with respect to the first nitride semiconductor layer. Then, in the interface region, the tetra-coordinated Al atoms are present by 30 at % or more and less than 50 at % based on the total number of Al atoms.

Abstract: There is a need to provide a small-sized memory interface circuit capable of adjusting timing between a strobe signal and a data signal without interrupting a normal memory access. An expected value acquisition latch latches write data in synchronization with a clock signal. A WDLL outputs a write strobe signal WDQS. An RDLL outputs a delayed write strobe signal WDQS_d. A read data latch latches looped-back write data in synchronization with the delayed write strobe signal WDQS_d. A comparator compares the read data latch with an output from the expected value acquisition latch. A register portion stores a delay value to be placed in the RDLL. A register control portion updates a delay value in the register portion in accordance with a comparison result. A delay selection portion places a delay value read from the register portion in the RDLL.

Abstract: A semiconductor device permitting the reduction of cost is disclosed. In a semiconductor package wherein electrode pads of a semiconductor chip and corresponding inner leads are electrically coupled with each other through a plurality of bonding wires, sensing wires (second and fourth bonding wires) are made thinner than other bonding wires (first and third bonding wires) coupled to inner leads same as those with the sensing wires coupled thereto, thereby reducing the cost of gold wires to attain the reduction in cost of the semiconductor package.

Abstract: A semiconductor integrated circuit includes a plurality of output transistors each controlling the magnitude of an output voltage relative to the magnitude of a load current according to a control value indicated by an impedance control signal applied to a control terminal, a voltage monitor circuit outputting an output voltage monitor value indicating a voltage value of the output voltage, and a control circuit controlling the magnitude of the control value according to the magnitude of an error value between a reference voltage indicating a target value of the output voltage and the output voltage monitor value, and controls based on the control value whether any of such transistors be brought to a conducting state. The control circuit increases a change step of the control value relative to the error value during a predetermined period according to prenotification signals for notifying a change of the load current in advance.

Abstract: The performances of a semiconductor device are improved. The device includes a first MISFET in which hafnium is added to the gate electrode side of a first gate insulation film including silicon oxynitride, and a second MISFET in which hafnium is added to the gate electrode side of a second gate insulation film including silicon oxynitride. The hafnium concentration in the second gate insulation film of the second MISFET is set smaller than the hafnium concentration in the first gate insulation film of the first MISFET; and the nitrogen concentration in the second gate insulation film of the second MISFET is set smaller than the nitrogen concentration in the first gate insulation film of the first MISFET. As a result, the threshold voltage of the second MISFET is adjusted to be smaller than the threshold voltage of the first MISFET.

Abstract: In a level shift circuit, input signals are input into gates of a first and a second MOS transistors whose sources are coupled to a first supply voltage VSS. Gates of a third and a fourth MOS transistors whose sources are coupled to a second supply voltage are coupled to drains of the second and the first MOS transistors. A first voltage generation circuit is coupled between the drains of the first and the third MOS transistors, and a second voltage generation circuit is coupled between the drains of the second and the fourth MOS transistors. The gate of the fifth MOS transistor is coupled to a connection node NDB, and the source of the fifth MOS transistor is coupled to the second supply voltage.

Abstract: A clock generator includes a counter unit receiving a reference clock signal to generate a timing signal, a selector receiving the timing signal to output a clock enable based on bit string data stored in a storage unit and a clock gate cell receiving the reference clock signal based on the clock, thinning some pulses out from the reference clock signal based on the clock enable so that a clock signal is maskable, and outputting an inter intermittent clock signal.

Abstract: A serial communication device has: a MAC (Media Access Control), a mask circuit and a buffer. The MAC conforms to Serial Media Independent Interface specification and outputs an identical segment data for plural times within a unit period. The mask circuit is configured to mask a predetermined segment data out of the plurality of identical segment data and to output the other segment data out of the plurality of identical segment data. The buffer is configured to receive the segment data output from the mask circuit and to output the received segment data to a physical layer device in synchronization with a clock signal.

Abstract: A lamination pattern having a control gate electrode, a first insulation film thereover, and a second insulation film thereover is formed over a semiconductor substrate. A memory gate electrode is formed adjacent to the lamination pattern. A gate insulation film is formed between the control gate and the semiconductor substrate. A fourth insulation film, including a lamination film of a silicon oxide film, a silicon nitride film, and another silicon oxide film, is formed between the memory gate electrode and the semiconductor substrate and between the lamination pattern and the memory gate electrode. At the sidewall on the side of the lamination pattern adjacent to the memory gate electrode, the first insulation film is retreated from the control gate electrode and the second insulation film, and the upper end corner portion of the control gate electrode is rounded.

Abstract: There is a need to provide an AD converter capable of reducing occurrence of a noise. An AD converter includes an operational amplifier and a clip circuit. The operational amplifier receives ramp voltage and voltage for an analog signal and allows output terminal voltage to transition from an H level to an L level when a change in the ramp voltage reaches the voltage for the analog signal. The clip circuit fixes an output terminal of the operational amplifier to clipping voltage after output voltage for the operational amplifier reaches threshold voltage for a latch circuit. Therefore, the AD converter can limit a range of output voltage, as a source of noise, for the operational amplifier and eliminate an unnecessary change in the output voltage after the threshold voltage for the latch circuit is reached.

Abstract: A control circuit generates a selection signal indicating a head area of an alignment buffer when the area is an unwritten area, and when the head area is a written area, successively performs comparison between a sequence number stored in the area and a sequence number of a target packet from a head to a tail to search a boundary area and generates a selection signal indicating the detected boundary area. When the boundary area could not be detected even when the search reaches the last written area, the control circuit generates a selection signal indicating the next area of the last written area. The writing circuit shifts data stored in each area by one area from the area indicated by the selection signal in a direction of the tail of the alignment buffer, and writes packet information of the target packet into the area indicated by the selection signal.

Abstract: Operation parallelism of a data processor is enhanced by floating-point inner product execution units compatible with single instruction multiple data (SIMD). An operating system that can significantly enhance the level of operation parallelism per instruction while maintaining efficiency of floating-point length-4 vector inner product execution units is implemented. The floating-point length-4 vector inner product execution units are defined in the minimum width (32 bits for single precision) even where an extensive operating system becomes available, and compose the inner product execution units to be compatible with SIMD. The mutually augmenting effects of the inner product execution units and SIMD-compatible composition enhances the level of operation parallelism dramatically.

Abstract: Provided is a semiconductor device including: a first memory that stores multiple instructions; a second memory that stores multiple data items; first and second buses; a microprocessor that fetches, through the first bus, an instruction at a specified address among the multiple instructions stored in the first memory, executes the instruction, and accesses the second memory through the second bus based on a result of the execution; and a trace information output unit that acquires, when a branch instruction is generated in the microprocessor, address information of the first memory specified before branching, and outputs the information as trace information. The trace information output from the trace information output unit is written into the second memory through the second bus in a period in which the microprocessor does not access the second memory during execution of the branch instruction.

Abstract: A PLL circuit includes: a phase comparator for detecting a phase difference between a reference signal and a feedback signal; a first charge pump for outputting a current Ipr according to a detection result of the phase comparator; a second charge pump for outputting a current Iint according to the detection result of the phase comparator; a filter for outputting a current Iprop from which a high frequency component of the Ipr is removed; an integrator for integrating the Iint; a voltage-current conversion circuit for outputting a current Ivi according to an integrated result of the integrator; and an oscillator that generates an oscillating signal of a frequency according to a current Iro, a sum of the Iprop and the Ivi, and feeds it back to the phase comparator.

Abstract: Disclosed is a semiconductor device provided with an active element in a multilayer interconnect layer and decreased in a chip area. A second interconnect layer is provided over a first interconnect layer. A first interlayer insulating layer is provided in the first interconnect layer. A semiconductor layer is provided in a second interconnect layer and in contact with the first interlayer insulating layer. A gate insulating film is provided over the semiconductor layer. A gate electrode is provided over the gate insulating film. At least two first vias are provided in the first interconnect layer and in contact by way of upper ends thereof with the semiconductor layer.

Abstract: A semiconductor device includes a first semiconductor chip operating at a first power supply voltage and a second semiconductor chip operating at a second power supply voltage lower than the first power supply voltage to supply the second power supply voltage to the first semiconductor chip. The semiconductor chips according to the present invention are conveniently used for fabrication of the semiconductor device. The first semiconductor chip includes an output circuit including a first transistor and a second transistor, interconnected in series and turned on or off complementarily. The output circuit outputs a signal to a first external output terminal. The first semiconductor chip also includes a third transistor connected in series with the first and second transistors and having a gate electrode connected to a second output terminal.

Abstract: A semiconductor device is provided which can change electrode pads of a semiconductor chip which are allocated to balls without any increase in the number of wires and without any change in a substrate. The semiconductor device includes a semiconductor chip having first and second electrode pads, and a package substrate on which the semiconductor chip is mounted. The package substrate includes a first stitch having a width larger than widths of first and second wires, a second stitch having a width larger than the widths of the first and second wires, a ball that can be coupled with an external, the first wire that couples the first stitch and the ball, and the second wire that couples the first stitch and the second stitch. A first bonding wire couples the first stitch and the first electrode pad, or the second stitch and the second electrode pad.