Abstract: A device is provided for time measurement of a clock-based signal comprising a sample stage comprising a switching device that is driven by a control signal and a capacitance (Cs), wherein the sample stage is arranged to transform an analog input signal in an analog output signal, the device further comprising an analog-to-digital converter to convert the analog output signal into a digital output signal, wherein the input signal applied to the sample stage is a reference signal and wherein the clock-based signal is applied to the control signal. Also, an according method is suggested.

Abstract: According to various embodiments, an electronic circuit includes a plurality of clock generators wherein each clock generator is configured to store a counter value, to receive a reference clock, to change the counter value in accordance with the reference clock and to generate at least one clock signal based on the counter value. The circuit also includes a comparator configured to receive, for each of at least two of the plurality of clock generators, the counter value and compare the received counter values and an error handling circuit configured to initiate an error handling based on the result of the comparison.

Abstract: Systems, methods, and circuits are provided for facilitating negative resistance margin testing in an oscillator circuit. An example oscillator circuit includes amplifier circuitry configured to be coupled in parallel with a resonator and variable resistance circuitry configured to, in response to a resistance control signal, adjust a resistance of the oscillator circuit.

Abstract: Systems, methods, and circuits are provided for facilitating negative resistance margin testing in an oscillator circuit. An example oscillator circuit includes amplifier circuitry configured to be coupled in parallel with a resonator and variable resistance circuitry configured to, in response to a resistance control signal, adjust a resistance of the oscillator circuit.

Abstract: A device is provided for time measurement of a clock-based signal comprising a sample stage comprising a switching device that is driven by a control signal and a capacitance (Cs), wherein the sample stage is arranged to transform an analog input signal in an analog output signal, the device further comprising an analog-to-digital converter to convert the analog output signal into a digital output signal, wherein the input signal applied to the sample stage is a reference signal and wherein the clock-based signal is applied to the control signal. Also, an according method is suggested.

Abstract: According to various embodiments, an electronic circuit includes a plurality of clock generators wherein each clock generator is configured to store a counter value, to receive a reference clock, to change the counter value in accordance with the reference clock and to generate at least one clock signal based on the counter value. The circuit also includes a comparator configured to receive, for each of at least two of the plurality of clock generators, the counter value and compare the received counter values and an error handling circuit configured to initiate an error handling based on the result of the comparison.

Abstract: A functional clock generator, including: an oscillator configured to generate an oscillator clock having an oscillator clock frequency; a control value generator configured to generate control values to ramp the oscillator clock frequency between a first frequency and a second, higher frequency; a Phase-Locked Loop (PLL) configured to generate a PLL clock having the second frequency; and a selector configured to switch between selecting the oscillator clock and the PLL clock as a functional clock when the oscillator clock frequency and the PLL clock frequency are substantially equal.

Abstract: In accordance with an embodiment, an electronic circuit includes at least five redundant circuit parts, which are configured to execute the same function in order to provide redundancy. The at least five redundant circuit parts are arranged in such a way that critical nodes of fewer than half of the circuit parts lie on an imaginary straight line.

Abstract: In accordance with an embodiment, an electronic circuit includes at least five redundant circuit parts, which are configured to execute the same function in order to provide redundancy. The at least five redundant circuit parts are arranged in such a way that critical nodes of fewer than half of the circuit parts lie on an imaginary straight line.

Abstract: Circuits and methods are provided for a signal path between circuit parts. During normal operation, a delay is deactivated. During a burn-in test, the delay is activated. In the deactivated state, a delay component may be disconnected from a supply voltage.

Abstract: Circuits and methods are provided for a signal path between circuit parts. During normal operation, a delay is deactivated. During a burn-in test, the delay is activated. In the deactivated state, a delay component may be disconnected from a supply voltage.

Abstract: The disclosure relates to an electronic memory system, and more specifically, to a system for storing data in an adjustably partitionable memory array, and a method to store data in an adjustably partitionable memory array. According to an embodiment of the disclosure, a system to store data in an adjustably partitionable memory array is provided, the system including a plurality of memory cells arranged in an array of rows and columns, a plurality of bit lines, and a plurality of switches, wherein each bit line is electrically coupled to a column of memory cells and each bit line comprises a switch configured to allow the respective bit line to be partitioned by opening of the switch.

Abstract: An embodiment integrated circuit (IC) clock distributor system includes a first IC. The first IC includes a clock synchronizer circuit and a clock generator circuit. The clock synchronizer circuit includes a first input coupled to a first clock transfer path including a replica delay of a portion of a first signal path included in an external IC. The clock synchronizer circuit also includes a second input coupled to a second clock transfer path. The clock generator circuit also includes an input coupled to an output of at least one of a reference oscillator and the clock synchronizer circuit. Delay of the second clock transfer path includes delay of the first signal path.

Abstract: A embodiment relates to a method for processing an erase counter comprising erase counter fields, the method comprising the steps of (i) determining an unused erase counter field; (ii) writing a selection code and an address information in the unused erase counter field, wherein the selection code and the address information are combined to determine at least one physical address of a memory.

Abstract: A method of detecting bit errors in a data storage device is provided, which includes comparing a first bit sequence accessed during a read out operation of the data storage device with a second bit sequence that corresponds to an expected memory state of the data storage device.

Abstract: A embodiment relates to a method for processing an erase counter comprising erase counter fields, the method comprising the steps of (i) determining an unused erase counter field; (ii) writing a selection code and an address information in the unused erase counter field, wherein the selection code and the address information are combined to determine at least one physical address of a memory.

Abstract: A method for incrementing an erase counter comprising several marker units is suggested, the method comprising the steps: (i) setting a marker unit in case a preceding marker unit was set; and (ii) not setting the marker unit in case the preceding marker unit was not set.

Abstract: A method of detecting bit errors in a data storage device is provided, which includes comparing a first bit sequence accessed during a read out operation of the data storage device with a second bit sequence that corresponds to an expected memory state of the data storage device.

Abstract: The disclosure relates to an electronic memory system, and more specifically, to a system for storing data in an adjustably partitionable memory array, and a method to store data in an adjustably partitionable memory array. According to an embodiment of the disclosure, a system to store data in an adjustably partitionable memory array is provided, the system including a plurality of memory cells arranged in an array of rows and columns, a plurality of bit lines, and a plurality of switches, wherein each bit line is electrically coupled to a column of memory cells and each bit line comprises a switch configured to allow the respective bit line to be partitioned by opening of the switch.

Abstract: A yaw rate sensor having a substrate and a seismic mass is described, in which the seismic mass is excitable to a working oscillation relative to the substrate via a drive unit, and a Coriolis deflection of the seismic mass is detectable relative to the substrate, in which the yaw rate sensor furthermore has an interrupt interface, the drive unit being configured to reduce a frequency and/or an amplitude of the working oscillation if an interrupt signal is present at the interrupt interface.