Abstract: A rotational rate sensor is provided having a substrate and having a seismic mass that is movable relative to the substrate, the seismic mass being capable of being excited by a drive unit to a working oscillation relative to the substrate, and a Coriolis deflection of the seismic mass perpendicular to the working oscillation being capable of being detected, the rotational rate sensor having an interface for sending out a sensor signal as a function of the Coriolis deflection, the drive unit being configured for the modification of a frequency and/or of an amplitude of the working oscillation when a control signal is present at the interface.

Abstract: A system and method is disclosed, including establishing of data connections between electronic devices. One embodiment provides a method for establishing a data connection between a first and a second electronic device, wherein establishing the data connection is authorized by executing at least one action with at least one physical tool.

Abstract: A memory device comprises a memory array and a processing device. The memory array is configured to store a graphic data set. The processing device is configured to initiate outputting of data of the graphic data set from the memory array and to combine the outputted data in response to a read request for providing a graphic content.

Abstract: An information transmitting apparatus is described. An interface includes a first input for a valid data word, a second input for an information to be transmitted, and an output, wherein the interface provides the data word or a data word recognizable as an invalid data word at the output, depending on the information. Accordingly, an information receiving apparatus comprises an interface comprising an input for a data word and an output for an information, wherein the interface derives the information depending on whether the data word is a valid data word or an invalid data word.

Abstract: A yaw rate sensor having a substrate and a seismic mass is described, in which the seismic mass is excitable to a working oscillation relative to the substrate via a drive unit, and a Coriolis deflection of the seismic mass is detectable relative to the substrate, in which the yaw rate sensor furthermore has an interrupt interface, the drive unit being configured to reduce a frequency and/or an amplitude of the working oscillation if an interrupt signal is present at the interrupt interface.

Abstract: A memory device has a first memory area and a second memory area. A method for operating the memory device includes a write access to the first memory area and a read access to the second memory area.

Abstract: A synchronization apparatus for data synchronization and method for data synchronization is disclosed. One embodiment provides clock signals which are phase-shifted relative to one another are used for synchronizing data packets in a serial-to-parallel conversion device in a write path and equally for synchronizing data packets in a parallel-to-serial conversion device in a read path.

Abstract: Two delay chains having in each case n series-connected unidirectional delay elements are provided for controllably delaying electrical signals between a circuit input and at least one circuit output. Each delay element is an active circuit with a fixed transit time. The input of the first delay element of the first chain is connected to the circuit input and the output of each delay element of the first delay chain is selectively connectable to the input of the (n?i+1)th delay element of the second delay chain via a respectively associated switch of a first group of switches, wherein i=1 . . . n is the ordinal number of the delay elements of the first delay chain. The output of the last delay element of the second chain is connected as a circuit output.

Abstract: An integrated circuit comprising a first terminal for exchanging signals; an evaluation unit coupled to the first terminal, the evaluation unit evaluating a signal level applied to the first terminal to determine whether or not the signal level corresponds to a predetermined signal level; and a switching unit coupled to the first terminal and to the evaluation unit, the switching unit admitting signal exchange via the first terminal if the evaluation unit does not determine the predetermined signal level, the switching unit cutting off signal exchange via the first terminal if the evaluation unit determines the predetermined signal level.

Abstract: A system and method is disclosed, including establishing of data connections between electronic devices. One embodiment provides a method for establishing a data connection between a first and a second electronic device, wherein establishing the data connection is authorized by executing at least one action with at least one physical tool.

Abstract: A storage device comprises a storage location, an interface coupled to the storage location, and a data conversion circuit coupled to the storage location and to the interface. The interface is configured for an exchange of data between the storage device and external circuitry coupled to the interface. The data conversion circuit is configured for converting data from a first data format to a second data format. The data conversion circuit is configured to convert at least one of data read from the storage location before they are transferred to the interface, and data received via the interface before they are written to the storage location.

Abstract: A memory device comprises a memory array and a processing device. The memory array is configured to store a graphic data set. The processing device is configured to initiate outputting of data of the graphic data set from the memory array and to combine the outputted data in response to a read request for providing a graphic content.

Abstract: An apparatus, method and system for comparing sample data with comparison date is disclosed. One embodiment provides a plurality of storage locations, an interface coupled to a plurality of storage locations for an exchange of data between the plurality of storage locations and external circuitry coupled to the interface, and a data comparator for comparing comparison data stored in the plurality of storage locations and sample data.

Abstract: A memory includes a plurality of first-in-first-out (FIFO) cells, an output pointer counter, a write training block and a multiplexer. The output pointer counter is for switching a value of a FIFO output pointer among the FIFO cells. The write training block is for generating information for shifting the FIFO output pointer based on data read from the FIFO cells. The multiplexer is for receiving the value of the FIFO output pointer from the output pointer counter. The multiplexer is also for receiving the multiplexing information for shifting the FIFO output pointer. The multiplexer is further for shifting the value of the FIFO output pointer based on the multiplexing information.

Abstract: A memory includes a plurality of first-in-first-out (FIFO) cells, an output pointer counter and a write training block. The output pointer counter is for switching a value of a FIFO output pointer among the FIFO cells. The write training block is for generating information for moving the FIFO output pointer based on data read from the FIFO cells.

Abstract: A control signal training system in an integrated circuit comprises a signal transmitting unit, the signal transmitting unit outputting control signals and sampling clock signals, the control signals and the sampling clock signals having a predetermined time phase with respect to each other, a signal receiving unit, the signal receiving unit latching control signals in relation to the sampling clock signals, and an evaluation unit connected to a reading unit and the signal transmitting unit, the evaluation unit determining concordance of the control signals outputted by the signal transmitting unit and the control signals read out by the reading unit from the signal receiving unit, the evaluation unit adapting the time phase between the control signals and the sampling clock signals step-by-step until concordance of the control signals outputted by the signal transmitting unit and the control signals read out the reading unit from the signal receiving unit is determined by the evaluation unit.

Abstract: An integrated circuit comprising a first terminal for exchanging signals; an evaluation unit coupled to the first terminal, the evaluation unit evaluating a signal level applied to the first terminal to determine whether or not the signal level corresponds to a predetermined signal level; and a switching unit coupled to the first terminal and to the evaluation unit, the switching unit admitting signal exchange via the first terminal if the evaluation unit does not determine the predetermined signal level, the switching unit cutting off signal exchange via the first terminal if the evaluation unit determines the predetermined signal level.

Abstract: A control signal training system in an integrated circuit comprises a signal transmitting unit, the signal transmitting unit outputting control signals and sampling clock signals, the control signals and the sampling clock signals having a predetermined time phase with respect to each other, a signal receiving unit, the signal receiving unit latching control signals in relation to the sampling clock signals, and an evaluation unit connected to a reading unit and the signal transmitting unit, the evaluation unit determining concordance of the control signals outputted by the signal transmitting unit and the control signals read out by the reading unit from the signal receiving unit, the evaluation unit adapting the time phase between the control signals and the sampling clock signals step-by-step until concordance of the control signals outputted by the signal transmitting unit and the control signals read out the reading unit from the signal receiving unit is determined by the evaluation unit.

Abstract: A memory device has a first memory area and a second memory area. A method for operating the memory device includes a write access to the first memory area and a read access to the second memory area.

Abstract: Apparatus and method of training a data transfer channel between a memory controller and a memory device connected to each other via a data signal transfer channel and an address signal transfer channel. The method comprises reading test data from a latching circuit connected to both an address signal input and a data or control signal output of the memory device or from a read only memory in the memory device, transferring a read signal representing the test data via the data signal transfer channel, detecting data from the read signal with a delay relative to a read clock signal; repeating the transferring, detecting steps, each time detecting the data at a different value of the delay; selecting a value of the delay, preferably a value at which the detected data equal the test data; and setting the delay to the selected value.